reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
21462 { 13342 /* v_add_nc_u16 */, AMDGPU::V_ADD_NC_U16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 21464 { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 21485 { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 21486 { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22371 { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22372 { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22380 { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22381 { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22452 { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22453 { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22458 { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22459 { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22527 { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22528 { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22533 { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22534 { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22592 { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22593 { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22739 { 26054 /* v_sub_nc_u16 */, AMDGPU::V_SUB_NC_U16_gfx10, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22741 { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, }, 22768 { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e64_vi, Convert__Reg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16 }, },