reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23581 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23582 { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23875 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23876 { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23879 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23880 { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },