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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc17606 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17607 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17614 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17615 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17622 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17623 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17630 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17631 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17638 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17639 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17646 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17647 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17654 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17655 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17662 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17663 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17670 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17671 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17678 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17679 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17686 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17687 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17694 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17695 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17702 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17703 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17710 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17711 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17718 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17719 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17726 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17727 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17734 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17735 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17742 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17743 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17750 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17751 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17758 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17759 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17766 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17767 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17774 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17775 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17782 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17783 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17790 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17791 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17798 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17799 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17806 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17807 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17871 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17872 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17879 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17880 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17887 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17888 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17895 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17896 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17903 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17904 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17911 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17912 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17919 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17920 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17927 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17928 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17935 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17936 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17943 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17944 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17951 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17952 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17959 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17960 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17967 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17968 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17975 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17976 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17983 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17984 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17991 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17992 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17999 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18000 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18007 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18008 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18015 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18016 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18023 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18024 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18031 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18032 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18039 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18040 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18047 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18048 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18055 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18056 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18063 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18064 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18071 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18072 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },