reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17847 { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, }, 17848 { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, }, 17849 { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, }, 17850 { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, }, 17851 { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, }, 17852 { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, }, 17853 { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, }, 17854 { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, }, 17855 { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, }, 17856 { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, }, 17857 { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, }, 17858 { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },