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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18075 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18076 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18077 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18082 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18083 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18084 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18089 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18090 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18091 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18096 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18097 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18098 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18103 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18104 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18105 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18110 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18111 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18114 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18115 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18118 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18119 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18273 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18274 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18275 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18280 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18281 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18282 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18287 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18288 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18289 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18294 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18295 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18296 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18301 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18302 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18303 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18449 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18450 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18453 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18454 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18457 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18458 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18461 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18462 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18465 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18466 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18469 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18470 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18499 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18500 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18503 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18504 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18507 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18508 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },