reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc
17602   { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17603   { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17610   { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17611   { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17618   { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17619   { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17626   { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17627   { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17634   { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17635   { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17642   { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17643   { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17650   { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17651   { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17658   { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17659   { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17666   { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17667   { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17674   { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17675   { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17682   { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17683   { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17690   { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17691   { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17698   { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17699   { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17706   { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17707   { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17714   { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17715   { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17722   { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17723   { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17730   { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17731   { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17738   { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17739   { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17746   { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17747   { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17754   { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17755   { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17762   { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17763   { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17770   { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17771   { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17778   { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17779   { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17786   { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17787   { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17794   { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17795   { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17802   { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17803   { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17867   { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17868   { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17875   { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17876   { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17883   { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17884   { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17891   { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17892   { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17899   { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17900   { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17907   { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17908   { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17915   { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17916   { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17923   { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17924   { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17931   { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17932   { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17939   { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17940   { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17947   { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17948   { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17955   { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17956   { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17963   { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17964   { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17971   { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17972   { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17979   { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17980   { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17987   { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17988   { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17995   { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17996   { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18003   { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18004   { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18011   { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18012   { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18019   { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18020   { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18027   { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18028   { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18035   { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18036   { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18043   { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18044   { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18051   { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18052   { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18059   { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18060   { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18067   { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18068   { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },