|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc17604 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17605 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17612 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17613 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17620 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17621 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17628 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17629 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17636 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17637 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17644 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17645 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17652 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17653 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17660 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17661 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17668 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17669 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17676 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17677 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17684 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17685 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17692 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17693 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17700 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17701 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17708 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17709 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17716 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17717 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17724 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17725 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17732 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17733 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17740 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17741 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17748 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17749 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17756 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17757 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17764 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17765 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17772 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17773 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17780 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17781 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17788 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17789 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17796 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17797 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17804 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17805 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17869 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17870 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17877 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17878 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17885 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17886 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17893 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17894 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17901 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17902 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17909 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17910 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17917 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17918 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17925 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17926 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17933 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17934 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17941 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17942 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17949 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17950 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17957 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17958 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17965 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17966 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17973 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17974 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17981 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17982 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17989 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17990 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17997 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17998 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18005 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18006 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18013 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18014 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18021 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18022 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18029 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18030 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18037 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18038 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18045 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18046 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18053 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18054 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18061 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18062 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18069 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18070 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },