reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
18081 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18088 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18095 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18102 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18109 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18279 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18286 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18293 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18300 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, }, 18307 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },