reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
13368 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13369 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13372 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13373 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13376 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13377 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13380 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13381 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13392 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13393 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13396 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, }, 13397 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },