reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc
12874   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12875   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12876   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12880   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12881   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12882   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12886   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12887   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12888   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12892   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12893   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12894   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12898   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12899   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12900   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12904   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12905   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12906   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12910   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12911   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12912   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12916   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12917   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12918   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12922   { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12923   { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12926   { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12927   { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12930   { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12931   { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12934   { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12935   { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12938   { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12939   { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12942   { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12943   { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12946   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12947   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12948   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12952   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12953   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12954   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12958   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12959   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12960   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12964   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12965   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12966   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12970   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12971   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12972   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12976   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12977   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12978   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12982   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12983   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12984   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12988   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12989   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12990   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12994   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12995   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12996   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13000   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13001   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13002   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13006   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13007   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13008   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13012   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13013   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13014   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13018   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13019   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13020   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13024   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13025   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13026   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13030   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13031   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13032   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13036   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13037   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13038   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13042   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13043   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13044   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13048   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13049   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13050   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },