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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc21539 { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21540 { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21541 { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21547 { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21548 { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21549 { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21562 { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21563 { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21564 { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21569 { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21570 { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21571 { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21585 { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21586 { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21587 { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21593 { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21594 { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21595 { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21609 { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21610 { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21611 { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21617 { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21618 { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21619 { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21633 { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21634 { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21635 { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21641 { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21642 { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21643 { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21665 { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21666 { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21667 { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21673 { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21674 { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21675 { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21681 { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21682 { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21683 { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21689 { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21690 { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21691 { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21752 { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21753 { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21754 { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21759 { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21760 { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21761 { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21864 { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21865 { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21872 { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21873 { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21887 { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21888 { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21894 { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21895 { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21910 { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21911 { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21918 { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21919 { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21934 { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21935 { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21942 { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21943 { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21958 { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21959 { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21966 { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21967 { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21990 { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21991 { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21998 { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21999 { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22006 { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22007 { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22014 { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22015 { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22077 { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22078 { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22084 { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22085 { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },