reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
21537 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21538 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21545 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21546 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21561 { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21568 { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21583 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21584 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21591 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21592 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21607 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21608 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21615 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21616 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21631 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21632 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21639 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21640 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21663 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21664 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21671 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21672 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21679 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21680 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21687 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e64_gfx10, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21688 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21751 { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21758 { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21862 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21870 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21885 { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21892 { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21908 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21916 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21932 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21940 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21956 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21964 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21988 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 21996 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 22004 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 22012 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 22075 { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, }, 22082 { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e64_vi, Convert__BoolReg1_0__VSrcB161_1__VSrcB161_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB16, MCK_VSrcB16 }, },