reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

21442   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21445   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21446   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21447   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21448   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21449   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21450   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21451   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21452   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21453   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21454   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21457   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21463   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21465   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21466   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21469   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21470   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21471   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21510   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21511   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21512   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21513   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21514   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21515   { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21516   { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21517   { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21521   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21522   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21523   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21524   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21525   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21526   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21527   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21528   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21529   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21530   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21531   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21532   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21533   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21534   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21535   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21536   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21553   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21554   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21555   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21556   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21557   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21558   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21559   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21560   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21575   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21576   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21577   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21578   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21579   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21580   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21581   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21582   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21599   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21600   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21601   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21602   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21603   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21604   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21605   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21606   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21623   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21624   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21625   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21626   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21627   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21628   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21629   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21630   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21647   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21648   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21649   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21650   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21651   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21652   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21653   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21654   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21655   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21656   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21657   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21658   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21659   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21660   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21661   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21662   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21695   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21696   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21697   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21698   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21699   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21700   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21701   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21702   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21703   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21704   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21705   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21706   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21707   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21708   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21709   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21710   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21711   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21712   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21713   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21714   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21715   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21716   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21717   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21718   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21719   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21720   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21721   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21722   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21723   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21724   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21725   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21726   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21727   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21728   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21729   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21730   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21731   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21732   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21733   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21734   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21735   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21736   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21737   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21738   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21739   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21740   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21741   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21742   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21743   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21744   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21745   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21746   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21747   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21748   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21749   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21750   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21765   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21766   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21767   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21768   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21769   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21770   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21771   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21772   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21773   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21774   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21775   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21776   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21777   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21778   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21779   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21780   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21781   { 16629 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21782   { 16661 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21783   { 16693 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21784   { 16723 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21785   { 16753 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21786   { 16785 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21787   { 16817 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21788   { 16849 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21789   { 16881 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21790   { 16913 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21791   { 16945 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21792   { 16977 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21793   { 17009 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21794   { 17041 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21795   { 17073 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21796   { 17107 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21797   { 17141 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21798   { 17175 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21799   { 17209 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21800   { 17243 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21801   { 17277 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21802   { 17311 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21803   { 17345 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21804   { 17379 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21805   { 17413 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21806   { 17447 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21807   { 17481 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21808   { 17511 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21809   { 17541 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21810   { 17575 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21811   { 17609 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21812   { 17639 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21813   { 17669 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21814   { 17703 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21815   { 17737 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21816   { 17769 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21817   { 17801 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21818   { 17835 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21819   { 17869 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21820   { 17903 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21821   { 17937 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21822   { 17971 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21823   { 18005 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21824   { 18039 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21825   { 18073 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21826   { 18107 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21827   { 18141 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21828   { 18177 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21829   { 18213 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21830   { 18249 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21831   { 18285 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21832   { 18321 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21833   { 18357 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21834   { 18393 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21835   { 18429 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21836   { 18465 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21837   { 18501 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21838   { 18537 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21839   { 18573 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21840   { 18605 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21841   { 18637 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21842   { 18673 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21843   { 18709 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21844   { 18741 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21845   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21846   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21847   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21848   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21849   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21850   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21851   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21852   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21853   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21854   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21855   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21856   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21857   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21858   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21859   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21860   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21877   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21878   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21879   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21880   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21881   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21882   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21883   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21884   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21899   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21900   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21901   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21902   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21903   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21904   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21905   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21906   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21923   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21924   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21925   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21926   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21927   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21928   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21929   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21930   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21947   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21948   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21949   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21950   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21951   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21952   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21953   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21954   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21971   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21972   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21973   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21974   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21975   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21976   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21977   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21978   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21979   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21980   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21981   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21982   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21983   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21984   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21985   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21986   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22019   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22020   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22021   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22022   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22023   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22024   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22025   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22026   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22027   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22028   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22029   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22030   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22031   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22032   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22033   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22034   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22035   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22036   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22037   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22038   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22039   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22040   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22041   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22042   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22043   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22044   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22045   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22046   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22047   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22048   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22049   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22050   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22051   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22052   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22053   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22054   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22055   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22056   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22057   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22058   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22059   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22060   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22061   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22062   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22063   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22064   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22065   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22066   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22067   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22068   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22069   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22070   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22071   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22072   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22073   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22074   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22089   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22090   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22091   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22092   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22093   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22094   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22095   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22096   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22097   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22098   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22099   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22100   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22101   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22102   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22103   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22104   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22105   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_BoolReg }, },
22106   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_BoolReg }, },
22107   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_BoolReg }, },
22114   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22115   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22116   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22117   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22118   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22119   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22120   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22121   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22122   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22123   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22124   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22125   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22126   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22127   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22128   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22129   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22130   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22131   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22132   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22133   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22134   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22135   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22136   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22137   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22138   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22139   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22140   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22141   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22142   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22143   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22144   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22145   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22146   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22147   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22148   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22149   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22150   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22151   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22152   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22153   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22154   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22155   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22156   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22157   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22158   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22159   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22160   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22161   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22162   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22163   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22164   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22165   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22166   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22167   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22168   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22169   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22170   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22171   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22172   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22173   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22174   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22175   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22176   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22177   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22178   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22179   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22180   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22181   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22182   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22183   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22184   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22185   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22186   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22187   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22188   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22195   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22196   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22197   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22199   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22200   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22204   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22205   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22206   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22210   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22211   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22212   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22214   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22215   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22216   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22217   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22218   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22219   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22220   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22221   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22222   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22223   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22224   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22225   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22226   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22227   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22228   { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22231   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22232   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22233   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22234   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22235   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22236   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22237   { 22651 /* v_div_fixup_legacy_f16 */, AMDGPU::V_DIV_FIXUP_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22238   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22239   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22240   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22241   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22242   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22243   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22264   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22265   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22266   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22267   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22268   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22269   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX7Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22270   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22280   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22281   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22282   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22283   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22284   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22285   { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22286   { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22287   { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22288   { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22291   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22292   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22293   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22294   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22295   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22296   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22297   { 23035 /* v_fma_legacy_f16 */, AMDGPU::V_FMA_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22304   { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22305   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22306   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22307   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22308   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22309   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22310   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22311   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22312   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22313   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22314   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22315   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22316   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22317   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22318   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22319   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22320   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22321   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22322   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22323   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22324   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22325   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22326   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22327   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22328   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22329   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22330   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22345   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22346   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22348   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22349   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22350   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22351   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22352   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22353   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22357   { 23485 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22358   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22359   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22360   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22361   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22362   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22363   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX7Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22364   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22387   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22388   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22389   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22390   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22391   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22392   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22393   { 23732 /* v_mad_f16 */, AMDGPU::V_MAD_F16_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22395   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22396   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22397   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22398   { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22403   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22404   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22405   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22406   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22407   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22408   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22409   { 23804 /* v_mad_legacy_f16 */, AMDGPU::V_MAD_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22410   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22411   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22412   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22413   { 23838 /* v_mad_legacy_i16 */, AMDGPU::V_MAD_LEGACY_I16_gfx9, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22414   { 23855 /* v_mad_legacy_u16 */, AMDGPU::V_MAD_LEGACY_U16_gfx9, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22418   { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22423   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22424   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22425   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22426   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22427   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22428   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22431   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22432   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22433   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22444   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22445   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22446   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22447   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22448   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22449   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22450   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22451   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22457   { 24134 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22471   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22472   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22473   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22506   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22507   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22508   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22519   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22520   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22521   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22522   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22523   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22524   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22525   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22526   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22532   { 24825 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22554   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22555   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22556   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22557   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22558   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22559   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22560   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22561   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22562   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22563   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22564   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22565   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22566   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22567   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22568   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22569   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22570   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22586   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22587   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22588   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22600   { 25163 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22601   { 25163 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22658   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22659   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22660   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22661   { 25577 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22662   { 25593 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22663   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22664   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22665   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22666   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22667   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22668   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22669   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22670   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22671   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22672   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22673   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22674   { 25655 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22675   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22676   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22677   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22678   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22679   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22680   { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22681   { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22682   { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22683   { 25743 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22684   { 25759 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22685   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22686   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22687   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22688   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22689   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22690   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22691   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22692   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22693   { 25805 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22694   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22695   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22696   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22697   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22698   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22699   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22700   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22701   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22702   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22703   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22704   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22705   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22709   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22710   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22711   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22712   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22713   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22714   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22715   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22716   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22717   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22718   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22719   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22720   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22721   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22724   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22727   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22728   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22729   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22730   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22731   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22732   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22733   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22736   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22740   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22742   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22743   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22746   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22747   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22748   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22751   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22752   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22753   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22756   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22759   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22760   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22761   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22762   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22763   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22764   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22765   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22766   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22767   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22769   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22770   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22771   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22772   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22773   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22774   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22775   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22776   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22777   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22778   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22779   { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22780   { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22781   { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },