reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

11080   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11081   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11082   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11090   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11094   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11095   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11096   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11097   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11098   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11099   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11100   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11101   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11102   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11110   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11111   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11112   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11120   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11124   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11125   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11126   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11127   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11128   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11129   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11130   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11131   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11132   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11136   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11137   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11138   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11146   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11150   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11151   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11152   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11153   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11154   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11155   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11156   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11157   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11158   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11162   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11163   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11164   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11172   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11176   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11177   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11178   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11179   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11180   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11181   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11182   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11183   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11184   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11188   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11189   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11190   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11198   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11202   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11203   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11204   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11205   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11206   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11207   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11208   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11209   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11210   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11214   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11215   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11216   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11224   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11228   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11229   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11230   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11231   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11232   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11233   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11234   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11235   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11236   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11240   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11241   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11242   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11250   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11254   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11255   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11256   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11257   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11258   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11259   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11260   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11261   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11262   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11266   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11267   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11268   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11276   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11280   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11281   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11282   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11283   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11284   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11285   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11286   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11287   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11288   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11291   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11292   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11298   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11301   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11302   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11303   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11304   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11305   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11306   { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11309   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11310   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11316   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11319   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11320   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11321   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11322   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11323   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11324   { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11327   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11328   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11334   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11337   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11338   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11339   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11340   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11341   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11342   { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11345   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11346   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11352   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11355   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11356   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11357   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11358   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11359   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11360   { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11363   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11364   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11370   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11373   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11374   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11375   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11376   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11377   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11378   { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11381   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11382   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11388   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11391   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11392   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11393   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11394   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11395   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11396   { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11400   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11401   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11402   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11410   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11414   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11415   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11416   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11417   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11418   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11419   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11420   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11421   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11422   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11426   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11427   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11428   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11436   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11440   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11441   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11442   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11443   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11444   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11445   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11446   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11447   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11448   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11452   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11453   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11454   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11462   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11466   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11467   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11468   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11469   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11470   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11471   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11472   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11473   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11474   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11478   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11479   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11480   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11488   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11492   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11493   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11494   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11495   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11496   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11497   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11498   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11499   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11500   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11508   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11509   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11510   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11518   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11522   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11523   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11524   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11525   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11526   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11527   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11528   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11529   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11530   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11534   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11535   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11536   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11544   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11548   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11549   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11550   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11551   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11552   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11553   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11554   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11555   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11556   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11560   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11561   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11562   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11570   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11574   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11575   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11576   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11577   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11578   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11579   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11580   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11581   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11582   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11586   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11587   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11588   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11596   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11600   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11601   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11602   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11603   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11604   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11605   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11606   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11607   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11608   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11612   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11613   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11614   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11622   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11626   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11627   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11628   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11629   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11630   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11631   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11632   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11633   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11634   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11638   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11639   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11640   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11648   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11652   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11653   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11654   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11655   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11656   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11657   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11658   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11659   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11660   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11664   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11665   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11666   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11674   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11678   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11679   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11680   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11681   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11682   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11683   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11684   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11685   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11686   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11690   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11691   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11692   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11700   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11704   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11705   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11706   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11707   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11708   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11709   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11710   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11711   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11712   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11716   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11717   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11718   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11726   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11730   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11731   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11732   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11733   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11734   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11735   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11736   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11737   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11738   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11742   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11743   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11744   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11752   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11756   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11757   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11758   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11759   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11760   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11761   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11762   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11763   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11764   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11768   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11769   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11770   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11778   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11782   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11783   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11784   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11785   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11786   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11787   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11788   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11789   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11790   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11794   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11795   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11796   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11804   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11808   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11809   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11810   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11811   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11812   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11813   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11814   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11815   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11816   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11820   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11821   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11822   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11830   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11834   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11835   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11836   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11837   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11838   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11839   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11840   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11841   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11842   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11846   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11847   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11848   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11856   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11860   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11861   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11862   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11863   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11864   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11865   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11866   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11867   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11868   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },