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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12698 { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12699 { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12700 { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12701 { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12702 { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12703 { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12704 { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12705 { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12706 { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12707 { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12708 { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12709 { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12790 { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12791 { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12792 { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12793 { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12794 { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12795 { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12796 { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12797 { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12798 { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12799 { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12800 { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12801 { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12832 { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12833 { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12834 { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12835 { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12836 { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12837 { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12838 { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12839 { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12840 { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12841 { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12842 { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12843 { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },