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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12516 { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12517 { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12518 { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12519 { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12520 { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12521 { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12522 { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12523 { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12524 { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12525 { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12526 { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_ImmOffset, MCK_gds }, },
12527 { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12528 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12529 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX7Only, { MCK_ImmOffset, MCK_gds }, },
12530 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12531 { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12532 { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_ImmOffset, MCK_gds }, },
12533 { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12693 { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12694 { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12695 { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },