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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12421 { 1726 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12422 { 1726 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12423 { 1737 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12424 { 1737 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12425 { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12426 { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12427 { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12428 { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12429 { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12430 { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12431 { 1782 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12432 { 1782 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12433 { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12434 { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12435 { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12436 { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12437 { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12438 { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12439 { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12440 { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12441 { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12442 { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12443 { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12444 { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12445 { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12446 { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12447 { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12448 { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12449 { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12450 { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12451 { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12452 { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12453 { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12454 { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12455 { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12456 { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12457 { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12458 { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12459 { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12460 { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12461 { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12462 { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12463 { 1936 /* ds_append */, AMDGPU::DS_APPEND_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12464 { 1936 /* ds_append */, AMDGPU::DS_APPEND_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12465 { 1936 /* ds_append */, AMDGPU::DS_APPEND_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12466 { 1946 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12467 { 1946 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12468 { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12469 { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12470 { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12471 { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12472 { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12473 { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12474 { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12475 { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12476 { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12477 { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12478 { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12479 { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12480 { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12481 { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12482 { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12483 { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12484 { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12485 { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12486 { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12487 { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12488 { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12489 { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12490 { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12491 { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12492 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12493 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12494 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12495 { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12496 { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12497 { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12498 { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12499 { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12500 { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12501 { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12502 { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12503 { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12504 { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12505 { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12506 { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12507 { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12508 { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12509 { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12510 { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12511 { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12512 { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12513 { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12514 { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12515 { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12534 { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12535 { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12536 { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12537 { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12538 { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12539 { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12540 { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12541 { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12542 { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12543 { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12544 { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12545 { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12546 { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12547 { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12548 { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12549 { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12550 { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12551 { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12552 { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12553 { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12554 { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12555 { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12556 { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12557 { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12558 { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12559 { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12560 { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12561 { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12562 { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12563 { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12564 { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12565 { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12566 { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12567 { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12568 { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12569 { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12570 { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12571 { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12572 { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12573 { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12574 { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12575 { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12576 { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12577 { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12578 { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12579 { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12580 { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12581 { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12582 { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12583 { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12584 { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12585 { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12586 { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12587 { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12588 { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12589 { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12590 { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12591 { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12592 { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12593 { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12594 { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12595 { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12596 { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12597 { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12598 { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12599 { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12600 { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12601 { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12602 { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12603 { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12604 { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12605 { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12606 { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12607 { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12608 { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12609 { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12610 { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12611 { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12612 { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12613 { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12614 { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12615 { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12616 { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12617 { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12618 { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12619 { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12620 { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12621 { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12622 { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12623 { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12624 { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12625 { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12626 { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12627 { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12628 { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12629 { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12630 { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12631 { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12632 { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12633 { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12634 { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12635 { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12636 { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12637 { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12638 { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12639 { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12640 { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12641 { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12642 { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12643 { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12644 { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12645 { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12646 { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12647 { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12648 { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12649 { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12650 { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12651 { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12652 { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12653 { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12654 { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12655 { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12656 { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12657 { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12658 { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12659 { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12660 { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12661 { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12662 { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12663 { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12664 { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12665 { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12666 { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12667 { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12668 { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12669 { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12670 { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12671 { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12675 { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12676 { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12677 { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12678 { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12679 { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12680 { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12681 { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12682 { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12683 { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12684 { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12685 { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12686 { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12687 { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12688 { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12689 { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12690 { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12691 { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12692 { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12696 { 3043 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12697 { 3043 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12710 { 3118 /* ds_read_addtid_b32 */, AMDGPU::DS_READ_ADDTID_B32_gfx10, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12711 { 3118 /* ds_read_addtid_b32 */, AMDGPU::DS_READ_ADDTID_B32_vi, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12712 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12713 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12714 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12715 { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12716 { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12717 { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12718 { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12719 { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12720 { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12721 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12722 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12723 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12724 { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12725 { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12726 { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12727 { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12728 { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12729 { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12730 { 3209 /* ds_read_i8_d16 */, AMDGPU::DS_READ_I8_D16_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12731 { 3209 /* ds_read_i8_d16 */, AMDGPU::DS_READ_I8_D16_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12732 { 3224 /* ds_read_i8_d16_hi */, AMDGPU::DS_READ_I8_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12733 { 3224 /* ds_read_i8_d16_hi */, AMDGPU::DS_READ_I8_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12734 { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12735 { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12736 { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12737 { 3254 /* ds_read_u16_d16 */, AMDGPU::DS_READ_U16_D16_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12738 { 3254 /* ds_read_u16_d16 */, AMDGPU::DS_READ_U16_D16_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12739 { 3270 /* ds_read_u16_d16_hi */, AMDGPU::DS_READ_U16_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12740 { 3270 /* ds_read_u16_d16_hi */, AMDGPU::DS_READ_U16_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12741 { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12742 { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12743 { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12744 { 3300 /* ds_read_u8_d16 */, AMDGPU::DS_READ_U8_D16_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12745 { 3300 /* ds_read_u8_d16 */, AMDGPU::DS_READ_U8_D16_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12746 { 3315 /* ds_read_u8_d16_hi */, AMDGPU::DS_READ_U8_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12747 { 3315 /* ds_read_u8_d16_hi */, AMDGPU::DS_READ_U8_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12748 { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12749 { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12750 { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12751 { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12752 { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12753 { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12754 { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12755 { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12756 { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12757 { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12758 { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12759 { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12760 { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12761 { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12762 { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12763 { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12764 { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12765 { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12766 { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12767 { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12768 { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12769 { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12770 { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12771 { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12772 { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12773 { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12774 { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12775 { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12776 { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12777 { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12778 { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12779 { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12780 { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12781 { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12782 { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12783 { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12784 { 3507 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
12785 { 3507 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
12786 { 3507 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
12787 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12788 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12789 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12802 { 3602 /* ds_write_addtid_b32 */, AMDGPU::DS_WRITE_ADDTID_B32_gfx10, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12803 { 3602 /* ds_write_addtid_b32 */, AMDGPU::DS_WRITE_ADDTID_B32_vi, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12804 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12805 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12806 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12807 { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12808 { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12809 { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12810 { 3649 /* ds_write_b16_d16_hi */, AMDGPU::DS_WRITE_B16_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12811 { 3649 /* ds_write_b16_d16_hi */, AMDGPU::DS_WRITE_B16_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12812 { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12813 { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12814 { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12815 { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12816 { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12817 { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12818 { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12819 { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12820 { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12821 { 3707 /* ds_write_b8_d16_hi */, AMDGPU::DS_WRITE_B8_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12822 { 3707 /* ds_write_b8_d16_hi */, AMDGPU::DS_WRITE_B8_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12823 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
12824 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
12825 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
12826 { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12827 { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12828 { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12829 { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12830 { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12831 { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12844 { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12845 { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12846 { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12847 { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12848 { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12849 { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12850 { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12851 { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12852 { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12853 { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12854 { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12855 { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12856 { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12857 { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12858 { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12859 { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12860 { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12861 { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12862 { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12863 { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12864 { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12865 { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12866 { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12867 { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },