reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc
23569   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23570   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23572   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23573   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23594   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23595   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23597   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23598   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23608   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23609   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23610   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w64_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23611   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23613   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23614   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23616   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23617   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23619   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23620   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23628   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23629   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23649   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23650   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23652   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23653   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23655   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23656   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23658   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX9Plus_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23659   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23661   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX9Plus_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23662   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23667   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23668   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23670   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23671   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23673   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23674   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23676   { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot5Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23677   { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot5Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23678   { 22797 /* v_dot2c_i32_i16 */, AMDGPU::V_DOT2C_I32_I16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot4Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23680   { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23681   { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23682   { 22884 /* v_dot8c_i32_i4 */, AMDGPU::V_DOT8C_I32_I4_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot3Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23684   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23685   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23687   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23688   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23689   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX7GFX8GFX9_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23700   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23701   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23703   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23704   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23706   { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23708   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDLInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23709   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23711   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23712   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23714   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23715   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23717   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23718   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23720   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23721   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23723   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23724   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23726   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23727   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23729   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23730   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23732   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23733   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23735   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23736   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23737   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX7GFX8GFX9_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23746   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23748   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23749   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23751   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23753   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23754   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23756   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23757   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23767   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23768   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23770   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23771   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23787   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23788   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23790   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23791   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23802   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23803   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23815   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23816   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23818   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23819   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23821   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23822   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23824   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23825   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23827   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23828   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23830   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23831   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23833   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23834   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23840   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23841   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23843   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23844   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23846   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23847   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23849   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23850   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23863   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23864   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23866   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23867   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23893   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23894   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23896   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23897   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23904   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23905   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23907   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23908   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },