reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
21456 { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, }, 22340 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx9_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, }, 22400 { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, }, 22420 { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, }, 22735 { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, }, 77622 { 23384 /* v_interp_p2_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX9Plus_isGFX9Only }, 77623 { 23384 /* v_interp_p2_f16 */, 18 /* 1, 4 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX9Plus_isGFX9Only }, 77624 { 23384 /* v_interp_p2_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX9Only }, 77625 { 23384 /* v_interp_p2_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_isGFX9Plus_isGFX9Only }, 77986 { 23752 /* v_mad_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX9Only }, 77987 { 23752 /* v_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX9Only }, 78030 { 23918 /* v_mad_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX9Only }, 78031 { 23918 /* v_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX9Only },