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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc17571 { 7896 /* s_andn1_saveexec_b64 */, AMDGPU::S_ANDN1_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17574 { 7936 /* s_andn1_wrexec_b64 */, AMDGPU::S_ANDN1_WREXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17587 { 8040 /* s_andn2_wrexec_b64 */, AMDGPU::S_ANDN2_WREXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17846 { 8695 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
18123 { 9556 /* s_call_b64 */, AMDGPU::S_CALL_B64_vi, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SoppBrTarget }, },
18309 { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18311 { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18313 { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18315 { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18373 { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18375 { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18421 { 11273 /* s_orn1_saveexec_b64 */, AMDGPU::S_ORN1_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18433 { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18435 { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18437 { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
21108 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21110 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21357 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21415 { 26272 /* v_swap_b32 */, AMDGPU::V_SWAP_B32_vi, Convert__Reg1_0__Reg1_1__Tie1_2_2__Tie0_1_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32 }, },
21439 { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21455 { 13281 /* v_add_i16 */, AMDGPU::V_ADD_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
21459 { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21482 { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22183 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22185 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22202 { 22439 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22208 { 22481 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22366 { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22370 { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22402 { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22422 { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22430 { 24018 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22435 { 24040 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22440 { 24062 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22470 { 24209 /* v_med3_f16 */, AMDGPU::V_MED3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22475 { 24231 /* v_med3_i16 */, AMDGPU::V_MED3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22480 { 24253 /* v_med3_u16 */, AMDGPU::V_MED3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22505 { 24709 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22510 { 24731 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22515 { 24753 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22609 { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22614 { 25211 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22707 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22734 { 26008 /* v_sub_i16 */, AMDGPU::V_SUB_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22783 { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
70872 { 9556 /* s_call_b64 */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX9Plus_isGFX8GFX9 },
72993 { 13281 /* v_add_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
72994 { 13281 /* v_add_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
76565 { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
76566 { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76597 { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
76598 { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76679 { 22439 /* v_cvt_pknorm_i16_f16 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
76680 { 22439 /* v_cvt_pknorm_i16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76681 { 22439 /* v_cvt_pknorm_i16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
76691 { 22481 /* v_cvt_pknorm_u16_f16 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
76692 { 22481 /* v_cvt_pknorm_u16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76693 { 22481 /* v_cvt_pknorm_u16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
77990 { 23762 /* v_mad_i32_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
77991 { 23762 /* v_mad_i32_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78034 { 23928 /* v_mad_u32_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78035 { 23928 /* v_mad_u32_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78056 { 24018 /* v_max3_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
78057 { 24018 /* v_max3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78058 { 24018 /* v_max3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78070 { 24040 /* v_max3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78071 { 24040 /* v_max3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78074 { 24062 /* v_max3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78075 { 24062 /* v_max3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78262 { 24209 /* v_med3_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
78263 { 24209 /* v_med3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78264 { 24209 /* v_med3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78276 { 24231 /* v_med3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78277 { 24231 /* v_med3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78280 { 24253 /* v_med3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78281 { 24253 /* v_med3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78345 { 24709 /* v_min3_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
78346 { 24709 /* v_min3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78347 { 24709 /* v_min3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78359 { 24731 /* v_min3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78360 { 24731 /* v_min3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78363 { 24753 /* v_min3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78364 { 24753 /* v_min3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78937 { 25211 /* v_pack_b32_f16 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX8GFX9 },
78938 { 25211 /* v_pack_b32_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78939 { 25211 /* v_pack_b32_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
79786 { 26008 /* v_sub_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
79787 { 26008 /* v_sub_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },