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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc17570 { 7896 /* s_andn1_saveexec_b64 */, AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17573 { 7936 /* s_andn1_wrexec_b64 */, AMDGPU::S_ANDN1_WREXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17586 { 8040 /* s_andn2_wrexec_b64 */, AMDGPU::S_ANDN2_WREXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17845 { 8695 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
18122 { 9556 /* s_call_b64 */, AMDGPU::S_CALL_B64_gfx10, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SoppBrTarget }, },
18308 { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18310 { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18312 { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18314 { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18372 { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18374 { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18420 { 11273 /* s_orn1_saveexec_b64 */, AMDGPU::S_ORN1_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18432 { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18434 { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18436 { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
21107 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21109 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21356 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21414 { 26272 /* v_swap_b32 */, AMDGPU::V_SWAP_B32_gfx10, Convert__Reg1_0__Reg1_1__Tie1_2_2__Tie0_1_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32 }, },
21438 { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21458 { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21460 { 13316 /* v_add_nc_i16 */, AMDGPU::V_ADD_NC_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
21461 { 13329 /* v_add_nc_i32 */, AMDGPU::V_ADD_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21481 { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22182 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22184 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22201 { 22439 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22207 { 22481 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22365 { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22369 { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22399 { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22401 { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22419 { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22421 { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22429 { 24018 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22434 { 24040 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22439 { 24062 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22469 { 24209 /* v_med3_f16 */, AMDGPU::V_MED3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22474 { 24231 /* v_med3_i16 */, AMDGPU::V_MED3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22479 { 24253 /* v_med3_u16 */, AMDGPU::V_MED3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22504 { 24709 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22509 { 24731 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22514 { 24753 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22608 { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22613 { 25211 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22706 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22737 { 26028 /* v_sub_nc_i16 */, AMDGPU::V_SUB_NC_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22738 { 26041 /* v_sub_nc_i32 */, AMDGPU::V_SUB_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22782 { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
70871 { 9556 /* s_call_b64 */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX9Plus_isGFX10Plus },
72997 { 13316 /* v_add_nc_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
72998 { 13316 /* v_add_nc_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
76563 { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
76564 { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76595 { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
76596 { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76676 { 22439 /* v_cvt_pknorm_i16_f16 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
76677 { 22439 /* v_cvt_pknorm_i16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76678 { 22439 /* v_cvt_pknorm_i16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
76688 { 22481 /* v_cvt_pknorm_u16_f16 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
76689 { 22481 /* v_cvt_pknorm_u16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76690 { 22481 /* v_cvt_pknorm_u16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
77984 { 23752 /* v_mad_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
77985 { 23752 /* v_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
77988 { 23762 /* v_mad_i32_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
77989 { 23762 /* v_mad_i32_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78028 { 23918 /* v_mad_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78029 { 23918 /* v_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78032 { 23928 /* v_mad_u32_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78033 { 23928 /* v_mad_u32_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78053 { 24018 /* v_max3_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
78054 { 24018 /* v_max3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78055 { 24018 /* v_max3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78068 { 24040 /* v_max3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78069 { 24040 /* v_max3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78072 { 24062 /* v_max3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78073 { 24062 /* v_max3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78259 { 24209 /* v_med3_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
78260 { 24209 /* v_med3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78261 { 24209 /* v_med3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78274 { 24231 /* v_med3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78275 { 24231 /* v_med3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78278 { 24253 /* v_med3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78279 { 24253 /* v_med3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78342 { 24709 /* v_min3_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
78343 { 24709 /* v_min3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78344 { 24709 /* v_min3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78357 { 24731 /* v_min3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78358 { 24731 /* v_min3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78361 { 24753 /* v_min3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78362 { 24753 /* v_min3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78934 { 25211 /* v_pack_b32_f16 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Plus_isGFX10Plus },
78935 { 25211 /* v_pack_b32_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78936 { 25211 /* v_pack_b32_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
79790 { 26028 /* v_sub_nc_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
79791 { 26028 /* v_sub_nc_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },