|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18856 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18869 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21377 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21390 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21395 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21403 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21444 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21468 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22726 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22745 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22750 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22758 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22796 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22802 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23035 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23041 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23044 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23049 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23067 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23077 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23516 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23526 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23529 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23537 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23566 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23580 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23860 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23874 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23878 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23890 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },