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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18855 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18868 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21376 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21389 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21394 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21402 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21446 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21469 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22230 { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22237 { 22651 /* v_div_fixup_legacy_f16 */, AMDGPU::V_DIV_FIXUP_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22290 { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22297 { 23035 /* v_fma_legacy_f16 */, AMDGPU::V_FMA_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22728 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22746 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22751 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22760 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
72891 { 13238 /* v_add_co_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX9Only },
72892 { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
73052 { 13388 /* v_addc_co_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX9Only },
73053 { 13388 /* v_addc_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
76821 { 22603 /* v_div_fixup_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Only },
76822 { 22603 /* v_div_fixup_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
76823 { 22603 /* v_div_fixup_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Only },
76842 { 22651 /* v_div_fixup_legacy_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Only },
76843 { 22651 /* v_div_fixup_legacy_f16 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX9Only },
76844 { 22651 /* v_div_fixup_legacy_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
77240 { 23005 /* v_fma_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Only },
77241 { 23005 /* v_fma_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
77242 { 23005 /* v_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Only },
77261 { 23035 /* v_fma_legacy_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX9Only },
77262 { 23035 /* v_fma_legacy_f16 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX9Only },
77263 { 23035 /* v_fma_legacy_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79693 { 25975 /* v_sub_co_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX9Only },
79694 { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79845 { 26100 /* v_subb_co_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX9Only },
79846 { 26100 /* v_subb_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79871 { 26125 /* v_subbrev_co_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX9Only },
79872 { 26125 /* v_subbrev_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79940 { 26175 /* v_subrev_co_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX9Only },
79941 { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },