reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12432 { 1782 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, }, 12467 { 1946 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, }, 12697 { 3043 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, }, 17595 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, }, 17597 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, }, 17599 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, }, 17601 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_128, MCK_ImmSMRDOffset20 }, }, 18231 { 10299 /* s_dcache_wb */, AMDGPU::S_DCACHE_WB_vi, Convert_NoOperands, AMFBS_isGFX8Plus_isGFX8GFX9, { }, }, 18232 { 10311 /* s_dcache_wb_vol */, AMDGPU::S_DCACHE_WB_VOL_vi, Convert_NoOperands, AMFBS_isGFX8Plus_isGFX8GFX9, { }, }, 18335 { 10828 /* s_memrealtime */, AMDGPU::S_MEMREALTIME_vi, Convert__Reg1_0, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_SReg_64_XEXEC }, }, 21491 { 13517 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, }, 22332 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22334 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22343 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22377 { 23617 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, }, 22386 { 23681 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, }, 22616 { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, }, 28941 { 1782 /* ds_add_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX8GFX9 }, 28942 { 1782 /* ds_add_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8Plus_isGFX8GFX9 }, 29010 { 1946 /* ds_bpermute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX8GFX9 }, 29441 { 3043 /* ds_permute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX8GFX9 }, 70122 { 8081 /* s_atc_probe */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8Plus_isGFX8GFX9 }, 70124 { 8093 /* s_atc_probe_buffer */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77578 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77579 { 23315 /* v_interp_mov_f32 */, 2 /* 1 */, MCK_InterpSlot, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77580 { 23315 /* v_interp_mov_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77581 { 23315 /* v_interp_mov_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77592 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77593 { 23332 /* v_interp_p1_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77594 { 23332 /* v_interp_p1_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77595 { 23332 /* v_interp_p1_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77637 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77638 { 23400 /* v_interp_p2_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77639 { 23400 /* v_interp_p2_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Plus_isGFX8GFX9 }, 77640 { 23400 /* v_interp_p2_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX8GFX9 },