reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12431 { 1782 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, }, 12466 { 1946 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, }, 12696 { 3043 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, }, 17594 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, }, 17596 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_gfx10, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, }, 17598 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, }, 17600 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx10, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_128, MCK_ImmSMRDOffset20 }, }, 18334 { 10828 /* s_memrealtime */, AMDGPU::S_MEMREALTIME_gfx10, Convert__Reg1_0, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_SReg_64_XEXEC }, }, 21490 { 13517 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, }, 22331 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22333 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22342 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22376 { 23617 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, }, 22385 { 23681 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, }, 22615 { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, }, 28939 { 1782 /* ds_add_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX10Plus }, 28940 { 1782 /* ds_add_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8Plus_isGFX10Plus }, 29009 { 1946 /* ds_bpermute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX10Plus }, 29440 { 3043 /* ds_permute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX10Plus }, 70121 { 8081 /* s_atc_probe */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8Plus_isGFX10Plus }, 70123 { 8093 /* s_atc_probe_buffer */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8Plus_isGFX10Plus }, 77574 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX10Plus }, 77575 { 23315 /* v_interp_mov_f32 */, 2 /* 1 */, MCK_InterpSlot, AMFBS_isGFX8Plus_isGFX10Plus }, 77576 { 23315 /* v_interp_mov_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Plus_isGFX10Plus }, 77577 { 23315 /* v_interp_mov_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX10Plus }, 77588 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX10Plus }, 77589 { 23332 /* v_interp_p1_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8Plus_isGFX10Plus }, 77590 { 23332 /* v_interp_p1_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Plus_isGFX10Plus }, 77591 { 23332 /* v_interp_p1_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX10Plus }, 77633 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX10Plus }, 77634 { 23400 /* v_interp_p2_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8Plus_isGFX10Plus }, 77635 { 23400 /* v_interp_p2_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Plus_isGFX10Plus }, 77636 { 23400 /* v_interp_p2_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX10Plus },