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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18866 { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18871 { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21387 { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21392 { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21397 { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21413 { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21466 { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21471 { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22228 { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22288 { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22743 { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22748 { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22753 { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22770 { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
73030 { 13378 /* v_add_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX8Only },
73031 { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
73066 { 13402 /* v_addc_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX8Only },
73067 { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
76815 { 22603 /* v_div_fixup_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX8Only },
76816 { 22603 /* v_div_fixup_f16 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Only },
76817 { 22603 /* v_div_fixup_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
77234 { 23005 /* v_fma_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX8Only },
77235 { 23005 /* v_fma_f16 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8Only },
77236 { 23005 /* v_fma_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
79823 { 26090 /* v_sub_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX8Only },
79824 { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
79859 { 26114 /* v_subb_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX8Only },
79860 { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
79885 { 26142 /* v_subbrev_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX8Only },
79886 { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
80066 { 26259 /* v_subrev_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX8Only },
80067 { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },