reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

11079   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11082   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11086   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11089   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11093   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11096   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11099   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11102   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11109   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11112   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11116   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11119   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11123   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11126   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11129   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11132   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11135   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11138   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11142   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11145   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11149   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11152   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11155   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11158   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11161   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11164   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11168   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11171   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11175   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11178   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11181   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11184   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11187   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11190   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11194   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11197   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11201   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11204   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11207   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11210   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11213   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11216   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11220   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11223   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11227   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11230   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11233   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11236   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11239   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11242   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11246   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11249   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11253   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11256   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11259   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11262   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11265   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11268   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11272   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11275   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11279   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11282   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11285   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11288   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11399   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11402   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11406   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11409   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11413   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11416   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11419   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11422   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11425   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11428   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11432   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11435   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11439   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11442   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11445   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11448   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11451   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11454   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11458   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11461   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11465   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11468   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11471   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11474   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11477   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11480   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11484   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11487   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11491   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11494   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11497   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11500   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11507   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11510   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11514   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11517   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11521   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11524   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11527   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11530   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11533   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11536   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11540   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11543   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11547   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11550   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11553   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11556   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11559   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11562   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11566   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11569   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11573   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11576   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11579   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11582   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11585   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11588   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11592   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11595   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11599   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11602   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11605   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11608   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11611   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11614   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11618   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11621   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11625   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11628   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11631   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11634   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11637   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11640   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11644   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11647   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11651   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11654   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11657   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11660   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11663   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11666   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11670   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11673   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11677   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11680   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11683   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11686   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11689   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11692   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11696   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11699   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11703   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11706   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11709   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11712   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11715   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11718   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11722   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11725   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11729   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11732   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11735   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11738   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11741   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11744   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11748   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11751   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11755   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11758   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11761   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11764   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11767   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11770   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11774   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11777   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11781   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11784   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11787   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11790   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11793   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11796   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11800   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11803   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11807   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11810   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11813   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11816   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11819   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11822   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11826   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11829   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11833   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11836   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11839   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11842   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11845   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11848   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11852   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11855   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11859   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11862   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11865   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11868   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11873   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11876   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11881   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11884   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11887   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11890   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11893   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11896   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11900   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11905   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11909   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11913   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11917   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11922   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11926   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11930   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11934   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11939   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11943   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11947   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12002   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12005   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12010   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12013   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12016   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12019   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12022   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12025   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12028   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12032   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12035   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12038   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12041   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12045   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12048   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12051   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12054   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12058   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12061   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12064   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12067   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12070   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12075   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12078   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12081   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12084   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12087   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12090   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12125   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12128   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12133   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12136   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12139   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12142   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12145   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12148   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12151   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12154   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12159   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12162   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12165   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12168   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12171   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12174   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12193   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12196   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12201   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12204   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12207   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12210   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12213   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12216   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12219   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12223   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12226   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12229   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12240   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12244   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12247   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12250   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12253   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12257   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12260   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12263   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12266   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12270   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12273   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12276   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12279   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12283   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12286   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12289   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12344   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12348   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12351   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12354   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12357   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12361   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12364   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12367   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12370   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12374   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12377   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12380   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12383   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12387   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12390   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12393   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12397   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12401   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12404   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12407   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12416   { 1674 /* buffer_wbinvl1 */, AMDGPU::BUFFER_WBINVL1_vi, Convert_NoOperands, AMFBS_isGFX8GFX9, {  }, },
12422   { 1726 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12424   { 1737 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12427   { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12430   { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12435   { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12438   { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12441   { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12444   { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12447   { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12450   { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12453   { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12456   { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12459   { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12462   { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12465   { 1936 /* ds_append */, AMDGPU::DS_APPEND_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12470   { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12473   { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12476   { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12479   { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12482   { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12485   { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12488   { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12491   { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12497   { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12500   { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12503   { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12506   { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12509   { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12512   { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12515   { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12518   { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12521   { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12524   { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12527   { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12533   { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12536   { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12539   { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12542   { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12545   { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12548   { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12551   { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12554   { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12557   { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12560   { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12563   { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12566   { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12569   { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12572   { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12575   { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12578   { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12581   { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12584   { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12587   { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12590   { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12593   { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12596   { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12599   { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12602   { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12605   { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12608   { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12611   { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12614   { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12617   { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12620   { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12623   { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12626   { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12629   { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12632   { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12635   { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12638   { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12641   { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12644   { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12647   { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12650   { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12653   { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12656   { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12659   { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12662   { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12665   { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12668   { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12671   { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12677   { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12680   { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12683   { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12686   { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12689   { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12692   { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12695   { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12700   { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12703   { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12706   { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12709   { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12717   { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12720   { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12726   { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12729   { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12736   { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12743   { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12750   { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12753   { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12756   { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12759   { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12762   { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12765   { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12768   { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12771   { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12774   { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12777   { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12780   { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12783   { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12786   { 3507 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
12792   { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12795   { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12798   { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12801   { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12809   { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12814   { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12817   { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12820   { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12828   { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12831   { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12834   { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12837   { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12840   { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12843   { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12846   { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12849   { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12852   { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12855   { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12858   { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12861   { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12864   { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12867   { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12870   { 3979 /* exp */, AMDGPU::EXP_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12873   { 3979 /* exp */, AMDGPU::EXP_DONE_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
17543   { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17546   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17549   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17552   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17555   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17558   { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
17561   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17564   { 7827 /* s_and_b64 */, AMDGPU::S_AND_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17568   { 7856 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17577   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17580   { 7967 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17584   { 8000 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17590   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17593   { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17813   { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17816   { 8531 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
17819   { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17822   { 8563 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
17825   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17828   { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17831   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17834   { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17837   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17840   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17849   { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17852   { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17855   { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17858   { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17863   { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17866   { 8794 /* s_brev_b64 */, AMDGPU::S_BREV_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18077   { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18080   { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18084   { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18087   { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18091   { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18094   { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18098   { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18101   { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18105   { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18108   { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18153   { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18156   { 9820 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18159   { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18176   { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18179   { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18182   { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18185   { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18188   { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18191   { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18194   { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18197   { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18200   { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18203   { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18206   { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18209   { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18213   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18216   { 10218 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18227   { 10269 /* s_dcache_inv */, AMDGPU::S_DCACHE_INV_vi, Convert_NoOperands, AMFBS_isGFX8GFX9, {  }, },
18240   { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18243   { 10419 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18246   { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18249   { 10447 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18252   { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18255   { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18258   { 10489 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18261   { 10505 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18265   { 10547 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64 }, },
18268   { 10559 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_vi, Convert__Reg1_0__ImmHwreg1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_ImmHwreg }, },
18275   { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18278   { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18282   { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18285   { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18289   { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18292   { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18296   { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18299   { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18303   { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18306   { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18318   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18321   { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18324   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18327   { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18330   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18333   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18338   { 10842 /* s_memtime */, AMDGPU::S_MEMTIME_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC }, },
18341   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18344   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18347   { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18350   { 10882 /* s_mov_b64 */, AMDGPU::S_MOV_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18353   { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18358   { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18361   { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18364   { 10947 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18367   { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18370   { 10975 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18378   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18381   { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18384   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18387   { 11064 /* s_nand_b64 */, AMDGPU::S_NAND_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18391   { 11095 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18395   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18398   { 11131 /* s_nor_b64 */, AMDGPU::S_NOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18402   { 11160 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18405   { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18408   { 11189 /* s_not_b64 */, AMDGPU::S_NOT_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18411   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18414   { 11208 /* s_or_b64 */, AMDGPU::S_OR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18418   { 11235 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18424   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18427   { 11304 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18431   { 11335 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18440   { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18443   { 11424 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18446   { 11439 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64 }, },
18483   { 11733 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64 }, },
18487   { 11755 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_vi, Convert__Reg1_1__ImmHwreg1_0, AMFBS_isGFX8GFX9, { MCK_ImmHwreg, MCK_SReg_32 }, },
18490   { 11768 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_vi, Convert__Imm1_1__ImmHwreg1_0, AMFBS_isGFX8GFX9, { MCK_ImmHwreg, MCK_Imm }, },
18494   { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18497   { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18513   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18516   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18519   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18524   { 11956 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18539   { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18542   { 12141 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18545   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18548   { 12162 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18552   { 12193 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18555   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18558   { 12223 /* s_xor_b64 */, AMDGPU::S_XOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18562   { 12252 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18701   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18705   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18708   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18711   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18714   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18718   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18721   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18724   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18727   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18731   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18734   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18737   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18740   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18744   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18747   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18750   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18801   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18805   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18808   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18811   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18814   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18818   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18821   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18824   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18827   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18831   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18834   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18837   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18840   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18844   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18847   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18850   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18861   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
18874   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18879   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18884   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
18889   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
18895   { 13631 /* v_clrexcp */, AMDGPU::V_CLREXCP_e32_vi, Convert_NoOperands, AMFBS_isGFX8GFX9, {  }, },
18915   { 13693 /* v_cmp_class_f32_e32 */, AMDGPU::V_CMP_CLASS_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
18927   { 13729 /* v_cmp_class_f64_e32 */, AMDGPU::V_CMP_CLASS_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VGPR_32 }, },
18947   { 13792 /* v_cmp_eq_f32_e32 */, AMDGPU::V_CMP_EQ_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
18959   { 13822 /* v_cmp_eq_f64_e32 */, AMDGPU::V_CMP_EQ_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
18979   { 13882 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
18991   { 13912 /* v_cmp_eq_i64_e32 */, AMDGPU::V_CMP_EQ_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19011   { 13972 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19023   { 14002 /* v_cmp_eq_u64_e32 */, AMDGPU::V_CMP_EQ_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19043   { 14059 /* v_cmp_f_f32_e32 */, AMDGPU::V_CMP_F_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19055   { 14087 /* v_cmp_f_f64_e32 */, AMDGPU::V_CMP_F_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19071   { 14143 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19083   { 14171 /* v_cmp_f_i64_e32 */, AMDGPU::V_CMP_F_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19099   { 14227 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19111   { 14255 /* v_cmp_f_u64_e32 */, AMDGPU::V_CMP_F_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19131   { 14314 /* v_cmp_ge_f32_e32 */, AMDGPU::V_CMP_GE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19143   { 14344 /* v_cmp_ge_f64_e32 */, AMDGPU::V_CMP_GE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19163   { 14404 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19175   { 14434 /* v_cmp_ge_i64_e32 */, AMDGPU::V_CMP_GE_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19195   { 14494 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19207   { 14524 /* v_cmp_ge_u64_e32 */, AMDGPU::V_CMP_GE_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19227   { 14584 /* v_cmp_gt_f32_e32 */, AMDGPU::V_CMP_GT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19239   { 14614 /* v_cmp_gt_f64_e32 */, AMDGPU::V_CMP_GT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19259   { 14674 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19271   { 14704 /* v_cmp_gt_i64_e32 */, AMDGPU::V_CMP_GT_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19291   { 14764 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19303   { 14794 /* v_cmp_gt_u64_e32 */, AMDGPU::V_CMP_GT_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19323   { 14854 /* v_cmp_le_f32_e32 */, AMDGPU::V_CMP_LE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19335   { 14884 /* v_cmp_le_f64_e32 */, AMDGPU::V_CMP_LE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19355   { 14944 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19367   { 14974 /* v_cmp_le_i64_e32 */, AMDGPU::V_CMP_LE_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19387   { 15034 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19399   { 15064 /* v_cmp_le_u64_e32 */, AMDGPU::V_CMP_LE_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19419   { 15124 /* v_cmp_lg_f32_e32 */, AMDGPU::V_CMP_LG_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19431   { 15154 /* v_cmp_lg_f64_e32 */, AMDGPU::V_CMP_LG_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19451   { 15214 /* v_cmp_lt_f32_e32 */, AMDGPU::V_CMP_LT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19463   { 15244 /* v_cmp_lt_f64_e32 */, AMDGPU::V_CMP_LT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19483   { 15304 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19495   { 15334 /* v_cmp_lt_i64_e32 */, AMDGPU::V_CMP_LT_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19515   { 15394 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19527   { 15424 /* v_cmp_lt_u64_e32 */, AMDGPU::V_CMP_LT_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19547   { 15484 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19559   { 15514 /* v_cmp_ne_i64_e32 */, AMDGPU::V_CMP_NE_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19579   { 15574 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19591   { 15604 /* v_cmp_ne_u64_e32 */, AMDGPU::V_CMP_NE_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19611   { 15667 /* v_cmp_neq_f32_e32 */, AMDGPU::V_CMP_NEQ_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19623   { 15699 /* v_cmp_neq_f64_e32 */, AMDGPU::V_CMP_NEQ_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19643   { 15763 /* v_cmp_nge_f32_e32 */, AMDGPU::V_CMP_NGE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19655   { 15795 /* v_cmp_nge_f64_e32 */, AMDGPU::V_CMP_NGE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19675   { 15859 /* v_cmp_ngt_f32_e32 */, AMDGPU::V_CMP_NGT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19687   { 15891 /* v_cmp_ngt_f64_e32 */, AMDGPU::V_CMP_NGT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19707   { 15955 /* v_cmp_nle_f32_e32 */, AMDGPU::V_CMP_NLE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19719   { 15987 /* v_cmp_nle_f64_e32 */, AMDGPU::V_CMP_NLE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19739   { 16051 /* v_cmp_nlg_f32_e32 */, AMDGPU::V_CMP_NLG_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19751   { 16083 /* v_cmp_nlg_f64_e32 */, AMDGPU::V_CMP_NLG_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19771   { 16147 /* v_cmp_nlt_f32_e32 */, AMDGPU::V_CMP_NLT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19783   { 16179 /* v_cmp_nlt_f64_e32 */, AMDGPU::V_CMP_NLT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19803   { 16237 /* v_cmp_o_f32_e32 */, AMDGPU::V_CMP_O_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19815   { 16265 /* v_cmp_o_f64_e32 */, AMDGPU::V_CMP_O_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19831   { 16321 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19843   { 16349 /* v_cmp_t_i64_e32 */, AMDGPU::V_CMP_T_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19859   { 16405 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19871   { 16433 /* v_cmp_t_u64_e32 */, AMDGPU::V_CMP_T_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
19891   { 16495 /* v_cmp_tru_f32_e32 */, AMDGPU::V_CMP_TRU_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19903   { 16527 /* v_cmp_tru_f64_e32 */, AMDGPU::V_CMP_TRU_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
19923   { 16585 /* v_cmp_u_f32_e32 */, AMDGPU::V_CMP_U_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
19935   { 16613 /* v_cmp_u_f64_e32 */, AMDGPU::V_CMP_U_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20207   { 18828 /* v_cmpx_class_f32_e32 */, AMDGPU::V_CMPX_CLASS_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20217   { 18866 /* v_cmpx_class_f64_e32 */, AMDGPU::V_CMPX_CLASS_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VGPR_32 }, },
20233   { 18933 /* v_cmpx_eq_f32_e32 */, AMDGPU::V_CMPX_EQ_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20243   { 18965 /* v_cmpx_eq_f64_e32 */, AMDGPU::V_CMPX_EQ_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20259   { 19029 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20269   { 19061 /* v_cmpx_eq_i64_e32 */, AMDGPU::V_CMPX_EQ_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20285   { 19125 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20295   { 19157 /* v_cmpx_eq_u64_e32 */, AMDGPU::V_CMPX_EQ_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20311   { 19218 /* v_cmpx_f_f32_e32 */, AMDGPU::V_CMPX_F_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20321   { 19248 /* v_cmpx_f_f64_e32 */, AMDGPU::V_CMPX_F_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20335   { 19308 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20345   { 19338 /* v_cmpx_f_i64_e32 */, AMDGPU::V_CMPX_F_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20359   { 19398 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20369   { 19428 /* v_cmpx_f_u64_e32 */, AMDGPU::V_CMPX_F_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20385   { 19491 /* v_cmpx_ge_f32_e32 */, AMDGPU::V_CMPX_GE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20395   { 19523 /* v_cmpx_ge_f64_e32 */, AMDGPU::V_CMPX_GE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20411   { 19587 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20421   { 19619 /* v_cmpx_ge_i64_e32 */, AMDGPU::V_CMPX_GE_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20437   { 19683 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20447   { 19715 /* v_cmpx_ge_u64_e32 */, AMDGPU::V_CMPX_GE_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20463   { 19779 /* v_cmpx_gt_f32_e32 */, AMDGPU::V_CMPX_GT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20473   { 19811 /* v_cmpx_gt_f64_e32 */, AMDGPU::V_CMPX_GT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20489   { 19875 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20499   { 19907 /* v_cmpx_gt_i64_e32 */, AMDGPU::V_CMPX_GT_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20515   { 19971 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20525   { 20003 /* v_cmpx_gt_u64_e32 */, AMDGPU::V_CMPX_GT_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20541   { 20067 /* v_cmpx_le_f32_e32 */, AMDGPU::V_CMPX_LE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20551   { 20099 /* v_cmpx_le_f64_e32 */, AMDGPU::V_CMPX_LE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20567   { 20163 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20577   { 20195 /* v_cmpx_le_i64_e32 */, AMDGPU::V_CMPX_LE_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20593   { 20259 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20603   { 20291 /* v_cmpx_le_u64_e32 */, AMDGPU::V_CMPX_LE_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20619   { 20355 /* v_cmpx_lg_f32_e32 */, AMDGPU::V_CMPX_LG_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20629   { 20387 /* v_cmpx_lg_f64_e32 */, AMDGPU::V_CMPX_LG_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20645   { 20451 /* v_cmpx_lt_f32_e32 */, AMDGPU::V_CMPX_LT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20655   { 20483 /* v_cmpx_lt_f64_e32 */, AMDGPU::V_CMPX_LT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20671   { 20547 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20681   { 20579 /* v_cmpx_lt_i64_e32 */, AMDGPU::V_CMPX_LT_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20697   { 20643 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20707   { 20675 /* v_cmpx_lt_u64_e32 */, AMDGPU::V_CMPX_LT_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20723   { 20739 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20733   { 20771 /* v_cmpx_ne_i64_e32 */, AMDGPU::V_CMPX_NE_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20749   { 20835 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20759   { 20867 /* v_cmpx_ne_u64_e32 */, AMDGPU::V_CMPX_NE_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20775   { 20934 /* v_cmpx_neq_f32_e32 */, AMDGPU::V_CMPX_NEQ_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20785   { 20968 /* v_cmpx_neq_f64_e32 */, AMDGPU::V_CMPX_NEQ_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20801   { 21036 /* v_cmpx_nge_f32_e32 */, AMDGPU::V_CMPX_NGE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20811   { 21070 /* v_cmpx_nge_f64_e32 */, AMDGPU::V_CMPX_NGE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20827   { 21138 /* v_cmpx_ngt_f32_e32 */, AMDGPU::V_CMPX_NGT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20837   { 21172 /* v_cmpx_ngt_f64_e32 */, AMDGPU::V_CMPX_NGT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20853   { 21240 /* v_cmpx_nle_f32_e32 */, AMDGPU::V_CMPX_NLE_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20863   { 21274 /* v_cmpx_nle_f64_e32 */, AMDGPU::V_CMPX_NLE_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20879   { 21342 /* v_cmpx_nlg_f32_e32 */, AMDGPU::V_CMPX_NLG_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20889   { 21376 /* v_cmpx_nlg_f64_e32 */, AMDGPU::V_CMPX_NLG_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20905   { 21444 /* v_cmpx_nlt_f32_e32 */, AMDGPU::V_CMPX_NLT_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20915   { 21478 /* v_cmpx_nlt_f64_e32 */, AMDGPU::V_CMPX_NLT_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20931   { 21540 /* v_cmpx_o_f32_e32 */, AMDGPU::V_CMPX_O_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
20941   { 21570 /* v_cmpx_o_f64_e32 */, AMDGPU::V_CMPX_O_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
20955   { 21630 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20965   { 21660 /* v_cmpx_t_i64_e32 */, AMDGPU::V_CMPX_T_I64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
20979   { 21720 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20989   { 21750 /* v_cmpx_t_u64_e32 */, AMDGPU::V_CMPX_T_U64_e32_vi, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB64, MCK_VReg_64 }, },
21005   { 21816 /* v_cmpx_tru_f32_e32 */, AMDGPU::V_CMPX_TRU_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
21015   { 21850 /* v_cmpx_tru_f64_e32 */, AMDGPU::V_CMPX_TRU_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
21031   { 21912 /* v_cmpx_u_f32_e32 */, AMDGPU::V_CMPX_U_F32_e32_vi, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF32, MCK_VGPR_32 }, },
21041   { 21942 /* v_cmpx_u_f64_e32 */, AMDGPU::V_CMPX_U_F64_e32_vi, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcF64, MCK_VReg_64 }, },
21044   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21055   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21058   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21065   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21068   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21071   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21074   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21077   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21080   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21083   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21086   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21089   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF32 }, },
21092   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32 }, },
21095   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32 }, },
21098   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21103   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21106   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21113   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21123   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21128   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21131   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21142   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21147   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21150   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21153   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21158   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21173   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21176   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21181   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21184   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21189   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21192   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21195   { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_vi, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
21198   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_vi, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21201   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_vi, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21204   { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21213   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21220   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21225   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21229   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21235   { 23982 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_vi, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, },
21239   { 24006 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_vi, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, },
21244   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21248   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21253   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21260   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21264   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21269   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21272   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21275   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21290   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21293   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21296   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21299   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21302   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21306   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21309   { 25176 /* v_nop */, AMDGPU::V_NOP_e32_vi, Convert_NoOperands, AMFBS_isGFX8GFX9, {  }, },
21312   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21315   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21325   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21328   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21331   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21336   { 25692 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_vi, Convert__Reg1_0__Reg1_1__SCSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_VRegOrLds_32, MCK_SCSrcB32 }, },
21341   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21351   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21354   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21363   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21368   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21371   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21382   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21408   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21421   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21427   { 26350 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_vi, Convert__Reg1_0__SCSrcB321_1__SCSrcB321_2__Tie0_1_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_SCSrcB32, MCK_SCSrcB32 }, },
21432   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21451   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21454   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21474   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21477   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21480   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21489   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21494   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21497   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21500   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21503   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21506   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21509   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21514   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21520   { 13631 /* v_clrexcp */, AMDGPU::V_CLREXCP_e64_vi, Convert_NoOperands, AMFBS_isGFX8GFX9, {  }, },
21525   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21528   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21533   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21536   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21541   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21544   { 13899 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21549   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21552   { 13989 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21557   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21560   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21564   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21567   { 14159 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21571   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21574   { 14243 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21579   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21582   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21587   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21590   { 14421 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21595   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21598   { 14511 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21603   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21606   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21611   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21614   { 14691 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21619   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21622   { 14781 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21627   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21630   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21635   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21638   { 14961 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21643   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21646   { 15051 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21651   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21654   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21659   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21662   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21667   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21670   { 15321 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21675   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21678   { 15411 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21683   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21686   { 15501 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21691   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21694   { 15591 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21699   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21702   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21707   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21710   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21715   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21718   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21723   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21726   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21731   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21734   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21739   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21742   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21747   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21750   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21754   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21757   { 16337 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21761   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21764   { 16421 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21769   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21772   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21777   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21780   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21849   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21852   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21857   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21860   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21865   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21868   { 19047 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21873   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21876   { 19143 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21881   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21884   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21888   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21891   { 19325 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21895   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21898   { 19415 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21903   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21906   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21911   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21914   { 19605 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21919   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21922   { 19701 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21927   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21930   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21935   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21938   { 19893 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21943   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21946   { 19989 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21951   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21954   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21959   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21962   { 20181 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21967   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21970   { 20277 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21975   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21978   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21983   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21986   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21991   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21994   { 20565 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21999   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22002   { 20661 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22007   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22010   { 20757 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22015   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22018   { 20853 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22023   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22026   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22031   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22034   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22039   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22042   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22047   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22050   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22055   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22058   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22063   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22066   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22071   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22074   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22078   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22081   { 21647 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22085   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22088   { 21737 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e64_vi, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22093   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22096   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22101   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22104   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22107   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_BoolReg }, },
22118   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22121   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22124   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22127   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22130   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22133   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22140   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22143   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22146   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22149   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22152   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22155   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22158   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22161   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22164   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22167   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22170   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22173   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22178   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22181   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22188   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22191   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22194   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22197   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22198   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
22200   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22203   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
22206   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22209   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
22212   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22213   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
22216   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22219   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22224   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22227   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22233   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22236   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22240   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22243   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22246   { 22704 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_vi, Convert__Reg1_0__BoolReg1_1__VSrcF321_2__VSrcF321_3__VSrcF321_4, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcF32, MCK_VSrcF32, MCK_VSrcF32 }, },
22249   { 22720 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_vi, Convert__Reg1_0__BoolReg1_1__VSrcF641_2__VSrcF641_3__VSrcF641_4, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcF64, MCK_VSrcF64, MCK_VSrcF64 }, },
22268   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22273   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22276   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22279   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22284   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22293   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22296   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22311   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22314   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22319   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22322   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22327   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22330   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22347   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
22350   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22353   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22356   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22362   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22375   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22384   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22390   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22397   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22405   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22412   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22425   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22433   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22438   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22443   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22448   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22451   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22456   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22462   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22465   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22468   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22473   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22478   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22483   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22508   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22513   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22518   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22523   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22526   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22531   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22537   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22540   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22543   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22556   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22562   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22567   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22570   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22573   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22576   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22579   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22582   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22585   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22588   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22591   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22596   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22599   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22604   { 25176 /* v_nop */, AMDGPU::V_NOP_e64_vi, Convert_NoOperands, AMFBS_isGFX8GFX9, {  }, },
22607   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22612   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22667   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22670   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22673   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22679   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22689   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22692   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22696   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22699   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22702   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22705   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22713   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22718   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22721   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22733   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22765   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22773   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22778   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22789   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
24161   { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24162   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24167   { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24168   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24175   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24176   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24181   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24182   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24189   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24190   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24195   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24196   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24201   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24202   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24207   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24208   { 0 /* buffer_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24221   { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24222   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24227   { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24228   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24235   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24236   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24241   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24242   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24249   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24250   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24255   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24256   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24261   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24262   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24267   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24268   { 40 /* buffer_atomic_add_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24273   { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24274   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24279   { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24280   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24287   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24288   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24293   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24294   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24301   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24302   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24307   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24308   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24313   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24314   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24319   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24320   { 61 /* buffer_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24325   { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24326   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24331   { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24332   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24339   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24340   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24345   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24346   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24353   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24354   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24359   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24360   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24365   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24366   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24371   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24372   { 79 /* buffer_atomic_and_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24377   { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24378   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24383   { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24384   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24391   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24392   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24397   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24398   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24405   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24406   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24411   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24412   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24417   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24418   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24423   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24424   { 100 /* buffer_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24429   { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24430   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24435   { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24436   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24443   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24444   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24449   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24450   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24457   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24458   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24463   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24464   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24469   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24470   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24475   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24476   { 122 /* buffer_atomic_cmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24481   { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24482   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24487   { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24488   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24495   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24496   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24501   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24502   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24509   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24510   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24515   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24516   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24521   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24522   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24527   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24528   { 147 /* buffer_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24533   { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24534   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24539   { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24540   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24547   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24548   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24553   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24554   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24561   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24562   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24567   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24568   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24573   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24574   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24579   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24580   { 165 /* buffer_atomic_dec_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24801   { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24802   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24807   { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24808   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24815   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24816   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24821   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24822   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24829   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24830   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24835   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24836   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24841   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24842   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24847   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24848   { 317 /* buffer_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24853   { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24854   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24859   { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24860   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24867   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24868   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24873   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24874   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24881   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24882   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24887   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24888   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24893   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24894   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24899   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24900   { 335 /* buffer_atomic_inc_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24905   { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24906   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24911   { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24912   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24919   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24920   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24925   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24926   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24933   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24934   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24939   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24940   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24945   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24946   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24951   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24952   { 356 /* buffer_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24957   { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24958   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24963   { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24964   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24971   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24972   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24977   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24978   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24985   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24986   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24991   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24992   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24997   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24998   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25003   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25004   { 373 /* buffer_atomic_or_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25017   { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25018   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25023   { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25024   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25031   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25032   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25037   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25038   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25045   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25046   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25051   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25052   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25057   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25058   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25063   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25064   { 418 /* buffer_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25069   { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25070   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25075   { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25076   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25083   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25084   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25089   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25090   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25097   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25098   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25103   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25104   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25109   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25110   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25115   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25116   { 437 /* buffer_atomic_smax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25121   { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25122   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25127   { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25128   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25135   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25136   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25141   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25142   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25149   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25150   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25155   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25156   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25161   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25162   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25167   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25168   { 459 /* buffer_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25173   { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25174   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25179   { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25180   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25187   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25188   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25193   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25194   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25201   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25202   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25207   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25208   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25213   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25214   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25219   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25220   { 478 /* buffer_atomic_smin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25225   { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25226   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25231   { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25232   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25239   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25240   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25245   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25246   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25253   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25254   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25259   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25260   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25265   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25266   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25271   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25272   { 500 /* buffer_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25277   { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25278   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25283   { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25284   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25291   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25292   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25297   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25298   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25305   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25306   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25311   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25312   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25317   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25318   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25323   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25324   { 518 /* buffer_atomic_sub_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25329   { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25330   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25335   { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25336   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25343   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25344   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25349   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25350   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25357   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25358   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25363   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25364   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25369   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25370   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25375   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25376   { 539 /* buffer_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25381   { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25382   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25387   { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25388   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25395   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25396   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25401   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25402   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25409   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25410   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25415   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25416   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25421   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25422   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25427   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25428   { 558 /* buffer_atomic_swap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25433   { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25434   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25439   { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25440   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25447   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25448   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25453   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25454   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25461   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25462   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25467   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25468   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25473   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25474   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25479   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25480   { 580 /* buffer_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25485   { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25486   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25491   { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25492   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25499   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25500   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25505   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25506   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25513   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25514   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25519   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25520   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25525   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25526   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25531   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25532   { 599 /* buffer_atomic_umax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25537   { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25538   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25543   { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25544   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25551   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25552   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25557   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25558   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25565   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25566   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25571   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25572   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25577   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25578   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25583   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25584   { 621 /* buffer_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25589   { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25590   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25595   { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25596   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25603   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25604   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25609   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25610   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25617   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25618   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25623   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25624   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25629   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25630   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25635   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25636   { 640 /* buffer_atomic_umin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25641   { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25642   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25647   { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25648   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25655   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25656   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25661   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25662   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25669   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25670   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25675   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25676   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25681   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25682   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25687   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25688   { 662 /* buffer_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25693   { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25694   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25699   { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25700   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25707   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25708   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25713   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25714   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25721   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25722   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25727   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25728   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25733   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25734   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25739   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25740   { 680 /* buffer_atomic_xor_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25751   { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25752   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25753   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25754   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25755   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25768   { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25769   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25770   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25771   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25772   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25773   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25795   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25796   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25797   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25798   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25799   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25812   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25813   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25814   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25815   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25816   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25817   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25828   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25829   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25830   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25831   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25832   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25845   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25846   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25847   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25848   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25849   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25850   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25861   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25862   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25863   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25864   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25865   { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25878   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25879   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25880   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25881   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25882   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25883   { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25901   { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25902   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25903   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25904   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25905   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25906   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25930   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25931   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25932   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25933   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25934   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25935   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25953   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25954   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25955   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25956   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25957   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25958   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25976   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25977   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
25978   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25979   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25980   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
25981   { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25999   { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26000   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26001   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26002   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26003   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26004   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26028   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26029   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26030   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26031   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26032   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26033   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26051   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26052   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26053   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26054   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26055   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26056   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26074   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26075   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26076   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26077   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26078   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26079   { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26097   { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26098   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26099   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26100   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26101   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26102   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26126   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26127   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26128   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26129   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26130   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26131   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26149   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26150   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26151   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26152   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26153   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26154   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26172   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26173   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26174   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26175   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26176   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26177   { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26500   { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26501   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26502   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26503   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26504   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26517   { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26518   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26519   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26520   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26521   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26522   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26544   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26545   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26546   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26547   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26548   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26561   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26562   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26563   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26564   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26565   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26566   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26577   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26578   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26579   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26580   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26581   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26594   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26595   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26596   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26597   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26598   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26599   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26610   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26611   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26612   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26613   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26614   { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26627   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26628   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26629   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26630   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26631   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26632   { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26645   { 964 /* buffer_load_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26646   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26647   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26648   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26649   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26650   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26669   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26670   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26671   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26672   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26673   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26674   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26687   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26688   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26689   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26690   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26691   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26692   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26705   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26706   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26707   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26708   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26709   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26710   { 964 /* buffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26723   { 986 /* buffer_load_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26724   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26725   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26726   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26727   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26728   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26747   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26748   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26749   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26750   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26751   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26752   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26765   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26766   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26767   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26768   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26769   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26770   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26783   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26784   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26785   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26786   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26787   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26788   { 986 /* buffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26801   { 1009 /* buffer_load_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26802   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26803   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26804   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26805   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26806   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26825   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26826   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26827   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26828   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26829   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26830   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26843   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26844   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26845   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26846   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26847   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26848   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26861   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26862   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26863   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26864   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26865   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26866   { 1009 /* buffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26877   { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26878   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26879   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26880   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26881   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26894   { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26895   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26896   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26897   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26898   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26899   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26921   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26922   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26923   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26924   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26925   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26938   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26939   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26940   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26941   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26942   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26943   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26954   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26955   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26956   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26957   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26958   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26971   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26972   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26973   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26974   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26975   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
26976   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26987   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26988   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
26989   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26990   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26991   { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27004   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27005   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27006   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27007   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27008   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27009   { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27212   { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27213   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27214   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27215   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27216   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27229   { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27230   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27231   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27232   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27233   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27234   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27256   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27257   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27258   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27259   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27260   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27273   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27274   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27275   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27276   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27277   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27278   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27289   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27290   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27291   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27292   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27293   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27306   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27307   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27308   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27309   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27310   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27311   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27322   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27323   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27324   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27325   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27326   { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27339   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27340   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27341   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27342   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27343   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27344   { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27355   { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27356   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27357   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27358   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27359   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27372   { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27373   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27374   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27375   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27376   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27377   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27399   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27400   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27401   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27402   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27403   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27416   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27417   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27418   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27419   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27420   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27421   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27432   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27433   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27434   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27435   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27436   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27449   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27450   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27451   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27452   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27453   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27454   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27465   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27466   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27467   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27468   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27469   { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27482   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27483   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27484   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27485   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27486   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27487   { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27594   { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27595   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27596   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27597   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27598   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27611   { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27612   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27613   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27614   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27615   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27616   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27638   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27639   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27640   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27641   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27642   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27655   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27656   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27657   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27658   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27659   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27660   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27671   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27672   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27673   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27674   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27675   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27688   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27689   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27690   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27691   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27692   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27693   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27704   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27705   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27706   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27707   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27708   { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27721   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27722   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27723   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27724   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27725   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27726   { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27739   { 1248 /* buffer_store_byte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27740   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27741   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27742   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27743   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27744   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27763   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27764   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27765   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27766   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27767   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27768   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27781   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27782   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27783   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27784   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27785   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27786   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27799   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27800   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27801   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27802   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27803   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27804   { 1248 /* buffer_store_byte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27865   { 1291 /* buffer_store_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27866   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27867   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27868   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27869   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27870   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27889   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27890   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27891   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27892   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27893   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27894   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27907   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27908   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27909   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27910   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27911   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27912   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27925   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27926   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27927   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27928   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27929   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27930   { 1291 /* buffer_store_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27943   { 1310 /* buffer_store_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27944   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27945   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27946   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27947   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27948   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27967   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27968   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27969   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27970   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27971   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27972   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27985   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27986   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
27987   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27988   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27989   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
27990   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28003   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28004   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28005   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28006   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28007   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28008   { 1310 /* buffer_store_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28021   { 1331 /* buffer_store_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28022   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28023   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28024   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28025   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28026   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28045   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28046   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28047   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28048   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28049   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28050   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28063   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28064   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28065   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28066   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28067   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28068   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28081   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28082   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28083   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28084   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28085   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28086   { 1331 /* buffer_store_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28099   { 1352 /* buffer_store_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28100   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28101   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28102   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28103   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28104   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28123   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28124   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28125   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28126   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28127   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28128   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28141   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28142   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28143   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28144   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28145   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28146   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28159   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28160   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28161   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28162   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28163   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28164   { 1352 /* buffer_store_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28489   { 1512 /* buffer_store_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28490   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28491   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28492   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28493   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28494   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28513   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28514   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28515   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28516   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28517   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28518   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28531   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28532   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28533   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28534   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28535   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28536   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28549   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28550   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28551   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28552   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28553   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28554   { 1512 /* buffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28567   { 1534 /* buffer_store_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28568   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28569   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28570   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28571   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28572   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28591   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28592   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28593   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28594   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28595   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28596   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28609   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28610   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28611   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28612   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28613   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28614   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28627   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28628   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28629   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28630   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28631   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28632   { 1534 /* buffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28645   { 1557 /* buffer_store_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28646   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28647   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28648   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28649   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28650   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28669   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28670   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28671   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28672   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28673   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28674   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28687   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28688   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28689   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28690   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28691   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28692   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28705   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28706   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28707   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28708   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28709   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28710   { 1557 /* buffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28723   { 1581 /* buffer_store_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28724   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28725   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28726   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28727   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28728   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28747   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28748   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28749   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28750   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28751   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28752   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28765   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28766   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28767   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28768   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28769   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28770   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28783   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28784   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28785   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28786   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28787   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28788   { 1581 /* buffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28805   { 1629 /* buffer_store_short */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28806   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28807   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28808   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28809   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28810   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28829   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28830   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28831   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28832   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28833   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28834   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28847   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28848   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28849   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28850   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28851   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28852   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28865   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28866   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
28867   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28868   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28869   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
28870   { 1629 /* buffer_store_short */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28921   { 1726 /* ds_add_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28922   { 1726 /* ds_add_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28925   { 1737 /* ds_add_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28926   { 1737 /* ds_add_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28931   { 1752 /* ds_add_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28932   { 1752 /* ds_add_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28937   { 1767 /* ds_add_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28938   { 1767 /* ds_add_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28947   { 1798 /* ds_add_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28948   { 1798 /* ds_add_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28953   { 1814 /* ds_add_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28954   { 1814 /* ds_add_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28959   { 1830 /* ds_add_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28960   { 1830 /* ds_add_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28965   { 1841 /* ds_add_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28966   { 1841 /* ds_add_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28971   { 1852 /* ds_and_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28972   { 1852 /* ds_and_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28977   { 1863 /* ds_and_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28978   { 1863 /* ds_and_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28983   { 1874 /* ds_and_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28984   { 1874 /* ds_and_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28989   { 1889 /* ds_and_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28990   { 1889 /* ds_and_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
28995   { 1904 /* ds_and_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28996   { 1904 /* ds_and_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29001   { 1920 /* ds_and_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29002   { 1920 /* ds_and_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29007   { 1936 /* ds_append */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29008   { 1936 /* ds_append */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29015   { 1962 /* ds_cmpst_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29016   { 1962 /* ds_cmpst_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29021   { 1975 /* ds_cmpst_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29022   { 1975 /* ds_cmpst_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29027   { 1988 /* ds_cmpst_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29028   { 1988 /* ds_cmpst_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29033   { 2001 /* ds_cmpst_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29034   { 2001 /* ds_cmpst_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29039   { 2014 /* ds_cmpst_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29040   { 2014 /* ds_cmpst_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29045   { 2031 /* ds_cmpst_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29046   { 2031 /* ds_cmpst_rtn_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29051   { 2048 /* ds_cmpst_rtn_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29052   { 2048 /* ds_cmpst_rtn_f32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29057   { 2065 /* ds_cmpst_rtn_f64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29058   { 2065 /* ds_cmpst_rtn_f64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29069   { 2104 /* ds_consume */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29070   { 2104 /* ds_consume */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29075   { 2115 /* ds_dec_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29076   { 2115 /* ds_dec_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29081   { 2130 /* ds_dec_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29082   { 2130 /* ds_dec_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29087   { 2145 /* ds_dec_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29088   { 2145 /* ds_dec_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29093   { 2161 /* ds_dec_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29094   { 2161 /* ds_dec_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29099   { 2177 /* ds_dec_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29100   { 2177 /* ds_dec_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29105   { 2188 /* ds_dec_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29106   { 2188 /* ds_dec_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29109   { 2199 /* ds_gws_barrier */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29112   { 2214 /* ds_gws_init */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29115   { 2226 /* ds_gws_sema_br */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29118   { 2241 /* ds_gws_sema_p */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29124   { 2279 /* ds_gws_sema_v */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29129   { 2293 /* ds_inc_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29130   { 2293 /* ds_inc_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29135   { 2308 /* ds_inc_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29136   { 2308 /* ds_inc_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29141   { 2323 /* ds_inc_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29142   { 2323 /* ds_inc_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29147   { 2339 /* ds_inc_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29148   { 2339 /* ds_inc_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29153   { 2355 /* ds_inc_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29154   { 2355 /* ds_inc_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29159   { 2366 /* ds_inc_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29160   { 2366 /* ds_inc_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29165   { 2377 /* ds_max_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29166   { 2377 /* ds_max_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29171   { 2388 /* ds_max_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29172   { 2388 /* ds_max_f64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29177   { 2399 /* ds_max_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29178   { 2399 /* ds_max_i32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29183   { 2410 /* ds_max_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29184   { 2410 /* ds_max_i64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29189   { 2421 /* ds_max_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29190   { 2421 /* ds_max_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29195   { 2436 /* ds_max_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29196   { 2436 /* ds_max_rtn_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29201   { 2451 /* ds_max_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29202   { 2451 /* ds_max_rtn_i32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29207   { 2466 /* ds_max_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29208   { 2466 /* ds_max_rtn_i64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29213   { 2481 /* ds_max_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29214   { 2481 /* ds_max_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29219   { 2496 /* ds_max_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29220   { 2496 /* ds_max_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29225   { 2511 /* ds_max_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29226   { 2511 /* ds_max_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29231   { 2527 /* ds_max_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29232   { 2527 /* ds_max_src2_f64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29237   { 2543 /* ds_max_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29238   { 2543 /* ds_max_src2_i32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29243   { 2559 /* ds_max_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29244   { 2559 /* ds_max_src2_i64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29249   { 2575 /* ds_max_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29250   { 2575 /* ds_max_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29255   { 2591 /* ds_max_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29256   { 2591 /* ds_max_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29261   { 2607 /* ds_max_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29262   { 2607 /* ds_max_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29267   { 2618 /* ds_max_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29268   { 2618 /* ds_max_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29273   { 2629 /* ds_min_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29274   { 2629 /* ds_min_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29279   { 2640 /* ds_min_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29280   { 2640 /* ds_min_f64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29285   { 2651 /* ds_min_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29286   { 2651 /* ds_min_i32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29291   { 2662 /* ds_min_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29292   { 2662 /* ds_min_i64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29297   { 2673 /* ds_min_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29298   { 2673 /* ds_min_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29303   { 2688 /* ds_min_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29304   { 2688 /* ds_min_rtn_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29309   { 2703 /* ds_min_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29310   { 2703 /* ds_min_rtn_i32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29315   { 2718 /* ds_min_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29316   { 2718 /* ds_min_rtn_i64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29321   { 2733 /* ds_min_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29322   { 2733 /* ds_min_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29327   { 2748 /* ds_min_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29328   { 2748 /* ds_min_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29333   { 2763 /* ds_min_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29334   { 2763 /* ds_min_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29339   { 2779 /* ds_min_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29340   { 2779 /* ds_min_src2_f64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29345   { 2795 /* ds_min_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29346   { 2795 /* ds_min_src2_i32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29351   { 2811 /* ds_min_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29352   { 2811 /* ds_min_src2_i64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29357   { 2827 /* ds_min_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29358   { 2827 /* ds_min_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29363   { 2843 /* ds_min_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29364   { 2843 /* ds_min_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29369   { 2859 /* ds_min_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29370   { 2859 /* ds_min_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29375   { 2870 /* ds_min_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29376   { 2870 /* ds_min_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29381   { 2881 /* ds_mskor_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29382   { 2881 /* ds_mskor_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29387   { 2894 /* ds_mskor_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29388   { 2894 /* ds_mskor_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29393   { 2907 /* ds_mskor_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29394   { 2907 /* ds_mskor_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29399   { 2924 /* ds_mskor_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29400   { 2924 /* ds_mskor_rtn_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29405   { 2948 /* ds_or_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29406   { 2948 /* ds_or_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29411   { 2958 /* ds_or_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29412   { 2958 /* ds_or_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29417   { 2968 /* ds_or_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29418   { 2968 /* ds_or_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29423   { 2982 /* ds_or_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29424   { 2982 /* ds_or_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29429   { 2996 /* ds_or_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29430   { 2996 /* ds_or_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29435   { 3011 /* ds_or_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29436   { 3011 /* ds_or_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29439   { 3026 /* ds_ordered_count */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29448   { 3058 /* ds_read2_b32 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29449   { 3058 /* ds_read2_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29450   { 3058 /* ds_read2_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29457   { 3071 /* ds_read2_b64 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29458   { 3071 /* ds_read2_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29459   { 3071 /* ds_read2_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29466   { 3084 /* ds_read2st64_b32 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29467   { 3084 /* ds_read2st64_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29468   { 3084 /* ds_read2st64_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29475   { 3101 /* ds_read2st64_b64 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29476   { 3101 /* ds_read2st64_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29477   { 3101 /* ds_read2st64_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29492   { 3150 /* ds_read_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29493   { 3150 /* ds_read_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29498   { 3162 /* ds_read_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29499   { 3162 /* ds_read_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29510   { 3186 /* ds_read_i16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29511   { 3186 /* ds_read_i16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29516   { 3198 /* ds_read_i8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29517   { 3198 /* ds_read_i8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29530   { 3242 /* ds_read_u16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29531   { 3242 /* ds_read_u16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29544   { 3289 /* ds_read_u8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29545   { 3289 /* ds_read_u8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29558   { 3333 /* ds_rsub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29559   { 3333 /* ds_rsub_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29564   { 3349 /* ds_rsub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29565   { 3349 /* ds_rsub_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29570   { 3365 /* ds_rsub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29571   { 3365 /* ds_rsub_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29576   { 3382 /* ds_rsub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29577   { 3382 /* ds_rsub_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29582   { 3399 /* ds_rsub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29583   { 3399 /* ds_rsub_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29588   { 3411 /* ds_rsub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29589   { 3411 /* ds_rsub_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29594   { 3423 /* ds_sub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29595   { 3423 /* ds_sub_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29600   { 3438 /* ds_sub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29601   { 3438 /* ds_sub_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29606   { 3453 /* ds_sub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29607   { 3453 /* ds_sub_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29612   { 3469 /* ds_sub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29613   { 3469 /* ds_sub_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29618   { 3485 /* ds_sub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29619   { 3485 /* ds_sub_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29624   { 3496 /* ds_sub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29625   { 3496 /* ds_sub_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29630   { 3507 /* ds_swizzle_b32 */, 4 /* 2 */, MCK_Swizzle, AMFBS_isGFX8GFX9 },
29631   { 3507 /* ds_swizzle_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29644   { 3538 /* ds_write2_b32 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29645   { 3538 /* ds_write2_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29646   { 3538 /* ds_write2_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29653   { 3552 /* ds_write2_b64 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29654   { 3552 /* ds_write2_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29655   { 3552 /* ds_write2_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29662   { 3566 /* ds_write2st64_b32 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29663   { 3566 /* ds_write2st64_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29664   { 3566 /* ds_write2st64_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29671   { 3584 /* ds_write2st64_b64 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29672   { 3584 /* ds_write2st64_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29673   { 3584 /* ds_write2st64_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29688   { 3636 /* ds_write_b16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29689   { 3636 /* ds_write_b16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29698   { 3669 /* ds_write_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29699   { 3669 /* ds_write_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29704   { 3682 /* ds_write_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29705   { 3682 /* ds_write_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29710   { 3695 /* ds_write_b8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29711   { 3695 /* ds_write_b8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29726   { 3739 /* ds_write_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29727   { 3739 /* ds_write_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29732   { 3757 /* ds_write_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29733   { 3757 /* ds_write_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29740   { 3775 /* ds_wrxchg2_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29741   { 3775 /* ds_wrxchg2_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29742   { 3775 /* ds_wrxchg2_rtn_b32 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29749   { 3794 /* ds_wrxchg2_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29750   { 3794 /* ds_wrxchg2_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29751   { 3794 /* ds_wrxchg2_rtn_b64 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29758   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29759   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29760   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29767   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX8GFX9 },
29768   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29769   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29774   { 3859 /* ds_wrxchg_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29775   { 3859 /* ds_wrxchg_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29780   { 3877 /* ds_wrxchg_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29781   { 3877 /* ds_wrxchg_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29786   { 3895 /* ds_xor_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29787   { 3895 /* ds_xor_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29792   { 3906 /* ds_xor_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29793   { 3906 /* ds_xor_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29798   { 3917 /* ds_xor_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29799   { 3917 /* ds_xor_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29804   { 3932 /* ds_xor_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29805   { 3932 /* ds_xor_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29810   { 3947 /* ds_xor_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29811   { 3947 /* ds_xor_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29816   { 3963 /* ds_xor_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29817   { 3963 /* ds_xor_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX8GFX9 },
29826   { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX8GFX9 },
29827   { 3979 /* exp */, 32 /* 5 */, MCK_ImmExpCompr, AMFBS_isGFX8GFX9 },
29828   { 3979 /* exp */, 64 /* 6 */, MCK_ImmExpVM, AMFBS_isGFX8GFX9 },
29829   { 3979 /* exp */, 1 /* 0 */, MCK_ImmExpTgt, AMFBS_isGFX8GFX9 },
29838   { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX8GFX9 },
29839   { 3979 /* exp */, 64 /* 6 */, MCK_ImmExpCompr, AMFBS_isGFX8GFX9 },
29840   { 3979 /* exp */, 128 /* 7 */, MCK_ImmExpVM, AMFBS_isGFX8GFX9 },
29841   { 3979 /* exp */, 1 /* 0 */, MCK_ImmExpTgt, AMFBS_isGFX8GFX9 },
70755   { 9380 /* s_buffer_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70756   { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70763   { 9380 /* s_buffer_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70764   { 9380 /* s_buffer_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70765   { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70773   { 9400 /* s_buffer_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70774   { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70781   { 9400 /* s_buffer_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70782   { 9400 /* s_buffer_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70783   { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70791   { 9423 /* s_buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70792   { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70799   { 9423 /* s_buffer_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70800   { 9423 /* s_buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70801   { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70809   { 9445 /* s_buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70810   { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70817   { 9445 /* s_buffer_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70818   { 9445 /* s_buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70819   { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70827   { 9467 /* s_buffer_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70828   { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70835   { 9467 /* s_buffer_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70836   { 9467 /* s_buffer_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70837   { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70902   { 10559 /* s_getreg_b32 */, 2 /* 1 */, MCK_ImmHwreg, AMFBS_isGFX8GFX9 },
70907   { 10626 /* s_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70908   { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70915   { 10626 /* s_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70916   { 10626 /* s_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70917   { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70925   { 10639 /* s_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70926   { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70933   { 10639 /* s_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70934   { 10639 /* s_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70935   { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70943   { 10655 /* s_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70944   { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70951   { 10655 /* s_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70952   { 10655 /* s_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70953   { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70961   { 10670 /* s_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70962   { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70969   { 10670 /* s_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70970   { 10670 /* s_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70971   { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70979   { 10685 /* s_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70980   { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70987   { 10685 /* s_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX8GFX9 },
70988   { 10685 /* s_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
70989   { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71059   { 11755 /* s_setreg_b32 */, 1 /* 0 */, MCK_ImmHwreg, AMFBS_isGFX8GFX9 },
71062   { 11768 /* s_setreg_imm32_b32 */, 1 /* 0 */, MCK_ImmHwreg, AMFBS_isGFX8GFX9 },
71798   { 12866 /* tbuffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71799   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71800   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71801   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71802   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71803   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71804   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71826   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71827   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71828   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71829   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71830   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71831   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71832   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71847   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71848   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71849   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71850   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71851   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71852   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71853   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71868   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71869   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71870   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71871   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71872   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71873   { 12866 /* tbuffer_load_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71874   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71889   { 12888 /* tbuffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71890   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71891   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71892   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71893   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71894   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71895   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71917   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71918   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71919   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71920   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71921   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71922   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71923   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71938   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71939   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71940   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71941   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71942   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71943   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71944   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71959   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71960   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71961   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71962   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71963   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71964   { 12888 /* tbuffer_load_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71965   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
71980   { 12911 /* tbuffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71981   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
71982   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71983   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71984   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
71985   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71986   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72008   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72009   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72010   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72011   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72012   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72013   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72014   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72029   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72030   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72031   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72032   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72033   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72034   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72035   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72050   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72051   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72052   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72053   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72054   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72055   { 12911 /* tbuffer_load_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72056   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72071   { 12935 /* tbuffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72072   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72073   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72074   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72075   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72076   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72077   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72099   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72100   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72101   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72102   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72103   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72104   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72105   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72120   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72121   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72122   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72123   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72124   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72125   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72126   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72141   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72142   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72143   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72144   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72145   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72146   { 12935 /* tbuffer_load_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72147   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72498   { 13074 /* tbuffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72499   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72500   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72501   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72502   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72503   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72504   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72526   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72527   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72528   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72529   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72530   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72531   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72532   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72547   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72548   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72549   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72550   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72551   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72552   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72553   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72568   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72569   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72570   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72571   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72572   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72573   { 13074 /* tbuffer_store_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72574   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72589   { 13097 /* tbuffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72590   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72591   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72592   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72593   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72594   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72595   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72617   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72618   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72619   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72620   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72621   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72622   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72623   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72638   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72639   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72640   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72641   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72642   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72643   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72644   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72659   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72660   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72661   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72662   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72663   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72664   { 13097 /* tbuffer_store_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72665   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72680   { 13121 /* tbuffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72681   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72682   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72683   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72684   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72685   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72686   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72708   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72709   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72710   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72711   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72712   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72713   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72714   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72729   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72730   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72731   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72732   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72733   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72734   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72735   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72750   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72751   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72752   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72753   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72754   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72755   { 13121 /* tbuffer_store_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72756   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72771   { 13146 /* tbuffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72772   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72773   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72774   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72775   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72776   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72777   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72799   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72800   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72801   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72802   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72803   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72804   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72805   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72820   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72821   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72822   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72823   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72824   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72825   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72826   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72841   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72842   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX8GFX9 },
72843   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72844   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72845   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX8GFX9 },
72846   { 13146 /* tbuffer_store_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72847   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX8GFX9 },
72950   { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
72951   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
72952   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
72990   { 13271 /* v_add_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
72991   { 13271 /* v_add_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
72992   { 13271 /* v_add_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73222   { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73223   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
73224   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73285   { 13677 /* v_cmp_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73286   { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73306   { 13713 /* v_cmp_class_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73307   { 13713 /* v_cmp_class_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73332   { 13779 /* v_cmp_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73333   { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73334   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73353   { 13809 /* v_cmp_eq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73354   { 13809 /* v_cmp_eq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73355   { 13809 /* v_cmp_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73372   { 13869 /* v_cmp_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73387   { 13899 /* v_cmp_eq_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73404   { 13959 /* v_cmp_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73419   { 13989 /* v_cmp_eq_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73444   { 14047 /* v_cmp_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73445   { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73446   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73465   { 14075 /* v_cmp_f_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73466   { 14075 /* v_cmp_f_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73467   { 14075 /* v_cmp_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73479   { 14131 /* v_cmp_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73494   { 14159 /* v_cmp_f_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73506   { 14215 /* v_cmp_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73521   { 14243 /* v_cmp_f_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73546   { 14301 /* v_cmp_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73547   { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73548   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73567   { 14331 /* v_cmp_ge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73568   { 14331 /* v_cmp_ge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73569   { 14331 /* v_cmp_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73586   { 14391 /* v_cmp_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73601   { 14421 /* v_cmp_ge_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73618   { 14481 /* v_cmp_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73633   { 14511 /* v_cmp_ge_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73658   { 14571 /* v_cmp_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73659   { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73660   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73679   { 14601 /* v_cmp_gt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73680   { 14601 /* v_cmp_gt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73681   { 14601 /* v_cmp_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73698   { 14661 /* v_cmp_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73713   { 14691 /* v_cmp_gt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73730   { 14751 /* v_cmp_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73745   { 14781 /* v_cmp_gt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73770   { 14841 /* v_cmp_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73771   { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73772   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73791   { 14871 /* v_cmp_le_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73792   { 14871 /* v_cmp_le_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73793   { 14871 /* v_cmp_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73810   { 14931 /* v_cmp_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73825   { 14961 /* v_cmp_le_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73842   { 15021 /* v_cmp_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73857   { 15051 /* v_cmp_le_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73882   { 15111 /* v_cmp_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73883   { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73884   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73903   { 15141 /* v_cmp_lg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73904   { 15141 /* v_cmp_lg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73905   { 15141 /* v_cmp_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73930   { 15201 /* v_cmp_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73931   { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
73932   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73951   { 15231 /* v_cmp_lt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73952   { 15231 /* v_cmp_lt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
73953   { 15231 /* v_cmp_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73970   { 15291 /* v_cmp_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
73985   { 15321 /* v_cmp_lt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74002   { 15381 /* v_cmp_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74017   { 15411 /* v_cmp_lt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74034   { 15471 /* v_cmp_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74049   { 15501 /* v_cmp_ne_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74066   { 15561 /* v_cmp_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74081   { 15591 /* v_cmp_ne_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74106   { 15653 /* v_cmp_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74107   { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74108   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74127   { 15685 /* v_cmp_neq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74128   { 15685 /* v_cmp_neq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74129   { 15685 /* v_cmp_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74154   { 15749 /* v_cmp_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74155   { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74156   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74175   { 15781 /* v_cmp_nge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74176   { 15781 /* v_cmp_nge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74177   { 15781 /* v_cmp_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74202   { 15845 /* v_cmp_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74203   { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74204   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74223   { 15877 /* v_cmp_ngt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74224   { 15877 /* v_cmp_ngt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74225   { 15877 /* v_cmp_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74250   { 15941 /* v_cmp_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74251   { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74252   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74271   { 15973 /* v_cmp_nle_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74272   { 15973 /* v_cmp_nle_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74273   { 15973 /* v_cmp_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74298   { 16037 /* v_cmp_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74299   { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74300   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74319   { 16069 /* v_cmp_nlg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74320   { 16069 /* v_cmp_nlg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74321   { 16069 /* v_cmp_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74346   { 16133 /* v_cmp_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74347   { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74348   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74367   { 16165 /* v_cmp_nlt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74368   { 16165 /* v_cmp_nlt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74369   { 16165 /* v_cmp_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74394   { 16225 /* v_cmp_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74395   { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74396   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74415   { 16253 /* v_cmp_o_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74416   { 16253 /* v_cmp_o_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74417   { 16253 /* v_cmp_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74429   { 16309 /* v_cmp_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74444   { 16337 /* v_cmp_t_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74456   { 16393 /* v_cmp_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74471   { 16421 /* v_cmp_t_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74496   { 16481 /* v_cmp_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74497   { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74498   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74517   { 16513 /* v_cmp_tru_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74518   { 16513 /* v_cmp_tru_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74519   { 16513 /* v_cmp_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74544   { 16573 /* v_cmp_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74545   { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74546   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74565   { 16601 /* v_cmp_u_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74566   { 16601 /* v_cmp_u_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74567   { 16601 /* v_cmp_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74780   { 18811 /* v_cmpx_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74781   { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74799   { 18849 /* v_cmpx_class_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74800   { 18849 /* v_cmpx_class_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74822   { 18919 /* v_cmpx_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74823   { 18919 /* v_cmpx_eq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74824   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74841   { 18951 /* v_cmpx_eq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74842   { 18951 /* v_cmpx_eq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74843   { 18951 /* v_cmpx_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74857   { 19015 /* v_cmpx_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74870   { 19047 /* v_cmpx_eq_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74884   { 19111 /* v_cmpx_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74897   { 19143 /* v_cmpx_eq_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74919   { 19205 /* v_cmpx_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74920   { 19205 /* v_cmpx_f_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
74921   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74938   { 19235 /* v_cmpx_f_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74939   { 19235 /* v_cmpx_f_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
74940   { 19235 /* v_cmpx_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74951   { 19295 /* v_cmpx_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74964   { 19325 /* v_cmpx_f_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74975   { 19385 /* v_cmpx_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
74988   { 19415 /* v_cmpx_f_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75010   { 19477 /* v_cmpx_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75011   { 19477 /* v_cmpx_ge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75012   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75029   { 19509 /* v_cmpx_ge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75030   { 19509 /* v_cmpx_ge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75031   { 19509 /* v_cmpx_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75045   { 19573 /* v_cmpx_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75058   { 19605 /* v_cmpx_ge_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75072   { 19669 /* v_cmpx_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75085   { 19701 /* v_cmpx_ge_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75107   { 19765 /* v_cmpx_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75108   { 19765 /* v_cmpx_gt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75109   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75126   { 19797 /* v_cmpx_gt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75127   { 19797 /* v_cmpx_gt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75128   { 19797 /* v_cmpx_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75142   { 19861 /* v_cmpx_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75155   { 19893 /* v_cmpx_gt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75169   { 19957 /* v_cmpx_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75182   { 19989 /* v_cmpx_gt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75204   { 20053 /* v_cmpx_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75205   { 20053 /* v_cmpx_le_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75206   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75223   { 20085 /* v_cmpx_le_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75224   { 20085 /* v_cmpx_le_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75225   { 20085 /* v_cmpx_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75239   { 20149 /* v_cmpx_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75252   { 20181 /* v_cmpx_le_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75266   { 20245 /* v_cmpx_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75279   { 20277 /* v_cmpx_le_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75301   { 20341 /* v_cmpx_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75302   { 20341 /* v_cmpx_lg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75303   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75320   { 20373 /* v_cmpx_lg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75321   { 20373 /* v_cmpx_lg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75322   { 20373 /* v_cmpx_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75344   { 20437 /* v_cmpx_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75345   { 20437 /* v_cmpx_lt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75346   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75363   { 20469 /* v_cmpx_lt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75364   { 20469 /* v_cmpx_lt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75365   { 20469 /* v_cmpx_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75379   { 20533 /* v_cmpx_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75392   { 20565 /* v_cmpx_lt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75406   { 20629 /* v_cmpx_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75419   { 20661 /* v_cmpx_lt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75433   { 20725 /* v_cmpx_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75446   { 20757 /* v_cmpx_ne_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75460   { 20821 /* v_cmpx_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75473   { 20853 /* v_cmpx_ne_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75495   { 20919 /* v_cmpx_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75496   { 20919 /* v_cmpx_neq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75497   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75514   { 20953 /* v_cmpx_neq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75515   { 20953 /* v_cmpx_neq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75516   { 20953 /* v_cmpx_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75538   { 21021 /* v_cmpx_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75539   { 21021 /* v_cmpx_nge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75540   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75557   { 21055 /* v_cmpx_nge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75558   { 21055 /* v_cmpx_nge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75559   { 21055 /* v_cmpx_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75581   { 21123 /* v_cmpx_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75582   { 21123 /* v_cmpx_ngt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75583   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75600   { 21157 /* v_cmpx_ngt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75601   { 21157 /* v_cmpx_ngt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75602   { 21157 /* v_cmpx_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75624   { 21225 /* v_cmpx_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75625   { 21225 /* v_cmpx_nle_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75626   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75643   { 21259 /* v_cmpx_nle_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75644   { 21259 /* v_cmpx_nle_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75645   { 21259 /* v_cmpx_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75667   { 21327 /* v_cmpx_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75668   { 21327 /* v_cmpx_nlg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75669   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75686   { 21361 /* v_cmpx_nlg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75687   { 21361 /* v_cmpx_nlg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75688   { 21361 /* v_cmpx_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75710   { 21429 /* v_cmpx_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75711   { 21429 /* v_cmpx_nlt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75712   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75729   { 21463 /* v_cmpx_nlt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75730   { 21463 /* v_cmpx_nlt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75731   { 21463 /* v_cmpx_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75753   { 21527 /* v_cmpx_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75754   { 21527 /* v_cmpx_o_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75755   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75772   { 21557 /* v_cmpx_o_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75773   { 21557 /* v_cmpx_o_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75774   { 21557 /* v_cmpx_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75785   { 21617 /* v_cmpx_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75798   { 21647 /* v_cmpx_t_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75809   { 21707 /* v_cmpx_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75822   { 21737 /* v_cmpx_t_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75844   { 21801 /* v_cmpx_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75845   { 21801 /* v_cmpx_tru_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75846   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75863   { 21835 /* v_cmpx_tru_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75864   { 21835 /* v_cmpx_tru_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75865   { 21835 /* v_cmpx_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75887   { 21899 /* v_cmpx_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75888   { 21899 /* v_cmpx_u_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
75889   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75906   { 21929 /* v_cmpx_u_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75907   { 21929 /* v_cmpx_u_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
75908   { 21929 /* v_cmpx_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75913   { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
75914   { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76014   { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76015   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76016   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76051   { 21993 /* v_cubeid_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76052   { 21993 /* v_cubeid_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76053   { 21993 /* v_cubeid_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76060   { 22006 /* v_cubema_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76061   { 22006 /* v_cubema_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76062   { 22006 /* v_cubema_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76069   { 22019 /* v_cubesc_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76070   { 22019 /* v_cubesc_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76071   { 22019 /* v_cubesc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76078   { 22032 /* v_cubetc_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76079   { 22032 /* v_cubetc_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76080   { 22032 /* v_cubetc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76089   { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76090   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76091   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76192   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX8GFX9 },
76193   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76194   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76229   { 22101 /* v_cvt_f32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
76230   { 22101 /* v_cvt_f32_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76231   { 22101 /* v_cvt_f32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76238   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76239   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76272   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76273   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76306   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76307   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76340   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76341   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76374   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76375   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76408   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76409   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76442   { 22211 /* v_cvt_f64_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76443   { 22211 /* v_cvt_f64_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76444   { 22211 /* v_cvt_f64_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76449   { 22225 /* v_cvt_f64_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76450   { 22225 /* v_cvt_f64_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76455   { 22239 /* v_cvt_f64_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76456   { 22239 /* v_cvt_f64_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76461   { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76462   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76527   { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76528   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76561   { 22299 /* v_cvt_i32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
76562   { 22299 /* v_cvt_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76633   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76634   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76667   { 22402 /* v_cvt_pk_u8_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76668   { 22402 /* v_cvt_pk_u8_f32 */, 12 /* 2, 3 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 },
76669   { 22402 /* v_cvt_pk_u8_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76673   { 22418 /* v_cvt_pkaccum_u8_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76674   { 22418 /* v_cvt_pkaccum_u8_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 },
76675   { 22418 /* v_cvt_pkaccum_u8_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76686   { 22460 /* v_cvt_pknorm_i16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76687   { 22460 /* v_cvt_pknorm_i16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76698   { 22502 /* v_cvt_pknorm_u16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76699   { 22502 /* v_cvt_pknorm_u16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76706   { 22523 /* v_cvt_pkrtz_f16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76707   { 22523 /* v_cvt_pkrtz_f16_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76708   { 22523 /* v_cvt_pkrtz_f16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76713   { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76714   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76779   { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76780   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76813   { 22589 /* v_cvt_u32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
76814   { 22589 /* v_cvt_u32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76830   { 22619 /* v_div_fixup_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76831   { 22619 /* v_div_fixup_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76832   { 22619 /* v_div_fixup_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76839   { 22635 /* v_div_fixup_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
76840   { 22635 /* v_div_fixup_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76841   { 22635 /* v_div_fixup_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76851   { 22674 /* v_div_fmas_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
76852   { 22674 /* v_div_fmas_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76853   { 22674 /* v_div_fmas_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76860   { 22689 /* v_div_fmas_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
76861   { 22689 /* v_div_fmas_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
76862   { 22689 /* v_div_fmas_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76865   { 22704 /* v_div_scale_f32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
76868   { 22720 /* v_div_scale_f64 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX8GFX9 },
77019   { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77020   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77021   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77194   { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77195   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77196   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77249   { 23015 /* v_fma_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77250   { 23015 /* v_fma_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77251   { 23015 /* v_fma_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77258   { 23025 /* v_fma_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
77259   { 23025 /* v_fma_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77260   { 23025 /* v_fma_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77372   { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77373   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77374   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77409   { 23192 /* v_fract_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
77410   { 23192 /* v_fract_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77411   { 23192 /* v_fract_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77448   { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77449   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77482   { 23244 /* v_frexp_exp_i32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
77483   { 23244 /* v_frexp_exp_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77528   { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77529   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77530   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77565   { 23298 /* v_frexp_mant_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
77566   { 23298 /* v_frexp_mant_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77567   { 23298 /* v_frexp_mant_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77572   { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77573   { 23315 /* v_interp_mov_f32 */, 2 /* 1 */, MCK_InterpSlot, AMFBS_isGFX8GFX9 },
77584   { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77587   { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77632   { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77699   { 23451 /* v_ldexp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77700   { 23451 /* v_ldexp_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 },
77701   { 23451 /* v_ldexp_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77702   { 23451 /* v_ldexp_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77711   { 23463 /* v_ldexp_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
77712   { 23463 /* v_ldexp_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 },
77713   { 23463 /* v_ldexp_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77714   { 23463 /* v_ldexp_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77762   { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77763   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77764   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77927   { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77928   { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77929   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77980   { 23742 /* v_mad_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
77981   { 23742 /* v_mad_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
77982   { 23742 /* v_mad_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77994   { 23776 /* v_mad_i32_i24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78010   { 23821 /* v_mad_legacy_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78011   { 23821 /* v_mad_legacy_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78012   { 23821 /* v_mad_legacy_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78038   { 23942 /* v_mad_u32_u24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78048   { 23982 /* v_madak_f32 */, 8 /* 3 */, MCK_KImmFP32, AMFBS_isGFX8GFX9 },
78052   { 24006 /* v_madmk_f32 */, 4 /* 2 */, MCK_KImmFP32, AMFBS_isGFX8GFX9 },
78065   { 24029 /* v_max3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78066   { 24029 /* v_max3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78067   { 24029 /* v_max3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78123   { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78124   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78125   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78163   { 24104 /* v_max_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
78164   { 24104 /* v_max_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78165   { 24104 /* v_max_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78271   { 24220 /* v_med3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78272   { 24220 /* v_med3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78273   { 24220 /* v_med3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78354   { 24720 /* v_min3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78355   { 24720 /* v_min3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78356   { 24720 /* v_min3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78412   { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78413   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78414   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78452   { 24795 /* v_min_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
78453   { 24795 /* v_min_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78454   { 24795 /* v_min_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78602   { 24946 /* v_mqsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78608   { 24979 /* v_msad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78656   { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78657   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78658   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78696   { 25009 /* v_mul_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
78697   { 25009 /* v_mul_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78698   { 25009 /* v_mul_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78794   { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
78795   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
78796   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79185   { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79186   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79187   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79222   { 25629 /* v_rcp_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
79223   { 25629 /* v_rcp_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79224   { 25629 /* v_rcp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79233   { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79234   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79235   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79311   { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79312   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79313   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79401   { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79402   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79403   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79438   { 25795 /* v_rsq_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
79439   { 25795 /* v_rsq_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79440   { 25795 /* v_rsq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79446   { 25822 /* v_sad_hi_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79449   { 25834 /* v_sad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79452   { 25844 /* v_sad_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79455   { 25854 /* v_sad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79535   { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79536   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79537   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79610   { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79611   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79612   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79647   { 25948 /* v_sqrt_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
79648   { 25948 /* v_sqrt_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79649   { 25948 /* v_sqrt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79752   { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
79753   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
79754   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79999   { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
80000   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
80001   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
80096   { 26297 /* v_trig_preop_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX8GFX9 },
80097   { 26297 /* v_trig_preop_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 },
80098   { 26297 /* v_trig_preop_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
80099   { 26297 /* v_trig_preop_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
80144   { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX8GFX9 },
80145   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX8GFX9 },
80146   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },