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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12420 { 1707 /* buffer_wbinvl1_vol */, AMDGPU::BUFFER_WBINVL1_VOL_vi, Convert_NoOperands, AMFBS_isGFX7Plus_isGFX8GFX9, { }, },
12494 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12530 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12674 { 2941 /* ds_nop */, AMDGPU::DS_NOP_vi, Convert_NoOperands, AMFBS_isGFX7Plus_isGFX8GFX9, { }, },
12714 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12723 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12789 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12806 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12825 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
18892 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21161 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21344 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21424 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21517 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22287 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22408 { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22428 { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22559 { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22660 { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22682 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22781 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
29063 { 2082 /* ds_condxchg32_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29064 { 2082 /* ds_condxchg32_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX8GFX9 },
29121 { 2255 /* ds_gws_sema_release_all */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29486 { 3137 /* ds_read_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29487 { 3137 /* ds_read_b128 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX8GFX9 },
29504 { 3174 /* ds_read_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29505 { 3174 /* ds_read_b96 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX8GFX9 },
29636 { 3522 /* ds_wrap_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29637 { 3522 /* ds_wrap_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX8GFX9 },
29682 { 3622 /* ds_write_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29683 { 3622 /* ds_write_b128 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX8GFX9 },
29720 { 3726 /* ds_write_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29721 { 3726 /* ds_write_b96 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX8GFX9 },
73259 { 13620 /* v_ceil_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX8GFX9 },
73260 { 13620 /* v_ceil_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
73261 { 13620 /* v_ceil_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
77231 { 22993 /* v_floor_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX8GFX9 },
77232 { 22993 /* v_floor_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
77233 { 22993 /* v_floor_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
77999 { 23790 /* v_mad_i64_i32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX7Plus_isGFX8GFX9 },
78000 { 23790 /* v_mad_i64_i32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
78043 { 23956 /* v_mad_u64_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX7Plus_isGFX8GFX9 },
78044 { 23956 /* v_mad_u64_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
78605 { 24964 /* v_mqsad_u32_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
79134 { 25560 /* v_qsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
79348 { 25731 /* v_rndne_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX8GFX9 },
79349 { 25731 /* v_rndne_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
79350 { 25731 /* v_rndne_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
80181 { 26338 /* v_trunc_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX8GFX9 },
80182 { 26338 /* v_trunc_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
80183 { 26338 /* v_trunc_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },