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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12419 { 1707 /* buffer_wbinvl1_vol */, AMDGPU::BUFFER_WBINVL1_VOL_gfx7, Convert_NoOperands, AMFBS_isGFX7Plus_isGFX7Only, { }, },
12493 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12529 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX7Only, { MCK_ImmOffset, MCK_gds }, },
12713 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12722 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12788 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12805 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12824 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
18891 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21160 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21343 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21423 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21516 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22286 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22407 { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22427 { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22558 { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22659 { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22681 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22780 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
29061 { 2082 /* ds_condxchg32_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29062 { 2082 /* ds_condxchg32_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX7Only },
29120 { 2255 /* ds_gws_sema_release_all */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29484 { 3137 /* ds_read_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29485 { 3137 /* ds_read_b128 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX7Only },
29502 { 3174 /* ds_read_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29503 { 3174 /* ds_read_b96 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX7Only },
29634 { 3522 /* ds_wrap_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29635 { 3522 /* ds_wrap_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX7Only },
29680 { 3622 /* ds_write_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29681 { 3622 /* ds_write_b128 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX7Only },
29718 { 3726 /* ds_write_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29719 { 3726 /* ds_write_b96 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX7Only },
73256 { 13620 /* v_ceil_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX7Only },
73257 { 13620 /* v_ceil_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX7Only },
73258 { 13620 /* v_ceil_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
77228 { 22993 /* v_floor_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX7Only },
77229 { 22993 /* v_floor_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX7Only },
77230 { 22993 /* v_floor_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
77997 { 23790 /* v_mad_i64_i32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX7Plus_isGFX7Only },
77998 { 23790 /* v_mad_i64_i32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
78041 { 23956 /* v_mad_u64_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX7Plus_isGFX7Only },
78042 { 23956 /* v_mad_u64_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
78604 { 24964 /* v_mqsad_u32_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
79133 { 25560 /* v_qsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
79345 { 25731 /* v_rndne_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX7Only },
79346 { 25731 /* v_rndne_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX7Only },
79347 { 25731 /* v_rndne_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
80178 { 26338 /* v_trunc_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX7Only },
80179 { 26338 /* v_trunc_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX7Only },
80180 { 26338 /* v_trunc_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },