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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12492 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12528 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12672 { 2941 /* ds_nop */, AMDGPU::DS_NOP_gfx10, Convert_NoOperands, AMFBS_isGFX7Plus_isGFX10Plus, { }, },
12712 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12721 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12787 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12804 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12823 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
18890 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21159 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21342 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21422 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21515 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22285 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22406 { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22426 { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22557 { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22658 { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22680 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22779 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
29059 { 2082 /* ds_condxchg32_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29060 { 2082 /* ds_condxchg32_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX10Plus },
29119 { 2255 /* ds_gws_sema_release_all */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29482 { 3137 /* ds_read_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29483 { 3137 /* ds_read_b128 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX10Plus },
29500 { 3174 /* ds_read_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29501 { 3174 /* ds_read_b96 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX10Plus },
29632 { 3522 /* ds_wrap_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29633 { 3522 /* ds_wrap_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX10Plus },
29678 { 3622 /* ds_write_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29679 { 3622 /* ds_write_b128 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX10Plus },
29716 { 3726 /* ds_write_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29717 { 3726 /* ds_write_b96 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX7Plus_isGFX10Plus },
73253 { 13620 /* v_ceil_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX10Plus },
73254 { 13620 /* v_ceil_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX10Plus },
73255 { 13620 /* v_ceil_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
77225 { 22993 /* v_floor_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX10Plus },
77226 { 22993 /* v_floor_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX10Plus },
77227 { 22993 /* v_floor_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
77995 { 23790 /* v_mad_i64_i32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX7Plus_isGFX10Plus },
77996 { 23790 /* v_mad_i64_i32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
78039 { 23956 /* v_mad_u64_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX7Plus_isGFX10Plus },
78040 { 23956 /* v_mad_u64_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
78603 { 24964 /* v_mqsad_u32_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
79132 { 25560 /* v_qsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
79342 { 25731 /* v_rndne_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX10Plus },
79343 { 25731 /* v_rndne_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX10Plus },
79344 { 25731 /* v_rndne_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
80175 { 26338 /* v_trunc_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX7Plus_isGFX10Plus },
80176 { 26338 /* v_trunc_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX7Plus_isGFX10Plus },
80177 { 26338 /* v_trunc_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },