reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12922 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12924 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12926 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12928 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12930 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12932 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12934 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12936 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12938 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12940 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12942 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12944 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 29938 { 4131 /* flat_atomic_fcmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29939 { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29942 { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29943 { 4131 /* flat_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29946 { 4152 /* flat_atomic_fcmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29947 { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29950 { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29951 { 4152 /* flat_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29954 { 4176 /* flat_atomic_fmax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29955 { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29958 { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29959 { 4176 /* flat_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29962 { 4193 /* flat_atomic_fmax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29963 { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29966 { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29967 { 4193 /* flat_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29970 { 4213 /* flat_atomic_fmin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29971 { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29974 { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29975 { 4213 /* flat_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29978 { 4230 /* flat_atomic_fmin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29979 { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only }, 29982 { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only }, 29983 { 4230 /* flat_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },