reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12923 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12925 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12927 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12929 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12931 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12933 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12935 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12937 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12939 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12941 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 12943 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 12945 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, }, 29940 { 4131 /* flat_atomic_fcmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29941 { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29944 { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29945 { 4131 /* flat_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29948 { 4152 /* flat_atomic_fcmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29949 { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29952 { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29953 { 4152 /* flat_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29956 { 4176 /* flat_atomic_fmax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29957 { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29960 { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29961 { 4176 /* flat_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29964 { 4193 /* flat_atomic_fmax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29965 { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29968 { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29969 { 4193 /* flat_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29972 { 4213 /* flat_atomic_fmin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29973 { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29976 { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29977 { 4213 /* flat_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29980 { 4230 /* flat_atomic_fmin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29981 { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus }, 29984 { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus }, 29985 { 4230 /* flat_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },