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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc11290 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11292 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11293 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11295 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11297 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11298 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11300 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11302 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11304 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11306 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11308 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11310 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11311 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11313 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11315 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11316 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11318 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11320 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11322 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11324 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11326 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11328 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11329 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11331 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11333 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11334 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11336 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11338 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11340 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11342 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11344 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11346 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11347 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11349 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11351 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11352 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11354 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11356 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11358 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11360 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11362 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11364 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11365 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11367 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11369 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11370 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11372 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11374 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11376 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11378 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11380 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11382 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11383 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11385 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11387 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11388 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11390 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11392 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11394 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11396 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
18875 { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21216 { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21221 { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21231 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21483 { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21484 { 13478 /* v_ashr_i64 */, AMDGPU::V_ASHR_I64_gfx6_gfx7, Convert__Reg1_0__VSrcB641_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32 }, },
22367 { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22368 { 23564 /* v_lshl_b64 */, AMDGPU::V_LSHL_B64_gfx6_gfx7, Convert__Reg1_0__VSrcB641_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32 }, },
22378 { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22379 { 23642 /* v_lshr_b64 */, AMDGPU::V_LSHR_B64_gfx6_gfx7, Convert__Reg1_0__VSrcB641_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32 }, },
22392 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22601 { 25163 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
24583 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24584 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24587 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24588 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24589 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24590 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24593 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24594 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24597 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24598 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24599 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24600 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24603 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24604 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24607 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24608 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24611 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24612 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24615 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24616 { 186 /* buffer_atomic_fcmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24619 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24620 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24623 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24624 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24625 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24626 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24629 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24630 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24633 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24634 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24635 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24636 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24639 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24640 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24643 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24644 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24647 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24648 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24651 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24652 { 209 /* buffer_atomic_fcmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24655 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24656 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24659 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24660 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24661 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24662 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24665 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24666 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24669 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24670 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24671 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24672 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24675 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24676 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24679 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24680 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24683 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24684 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24687 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24688 { 235 /* buffer_atomic_fmax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24691 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24692 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24695 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24696 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24697 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24698 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24701 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24702 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24705 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24706 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24707 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24708 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24711 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24712 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24715 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24716 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24719 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24720 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24723 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24724 { 254 /* buffer_atomic_fmax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24727 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24728 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24731 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24732 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24733 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24734 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24737 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24738 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24741 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24742 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24743 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24744 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24747 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24748 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24751 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24752 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24755 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24756 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24759 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24760 { 276 /* buffer_atomic_fmin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24763 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24764 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24767 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24768 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24769 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24770 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24773 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24774 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24777 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24778 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24779 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24780 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24783 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24784 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24787 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24788 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24791 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24792 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24795 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24796 { 295 /* buffer_atomic_fmin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
77952 { 23715 /* v_mac_legacy_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
77953 { 23715 /* v_mac_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
77954 { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
78876 { 25163 /* v_mullit_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
78877 { 25163 /* v_mullit_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
78878 { 25163 /* v_mullit_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },