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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc11289 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11291 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11294 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11296 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11299 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11301 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11303 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11305 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11307 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11309 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11312 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11314 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11317 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11319 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11321 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11323 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11325 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11327 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11330 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11332 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11335 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11337 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11339 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11341 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11343 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11345 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11348 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11350 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11353 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11355 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11357 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11359 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11361 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11363 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11366 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11368 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11371 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11373 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11375 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11377 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11379 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11381 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11384 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11386 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11389 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11391 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11393 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11395 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
21230 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
22391 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22600 { 25163 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
24581 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24582 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24585 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24586 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24591 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24592 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24595 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24596 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24601 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24602 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24605 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24606 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24609 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24610 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24613 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24614 { 186 /* buffer_atomic_fcmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24617 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24618 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24621 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24622 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24627 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24628 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24631 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24632 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24637 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24638 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24641 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24642 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24645 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24646 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24649 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24650 { 209 /* buffer_atomic_fcmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24653 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24654 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24657 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24658 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24663 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24664 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24667 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24668 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24673 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24674 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24677 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24678 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24681 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24682 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24685 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24686 { 235 /* buffer_atomic_fmax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24689 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24690 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24693 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24694 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24699 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24700 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24703 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24704 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24709 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24710 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24713 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24714 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24717 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24718 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24721 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24722 { 254 /* buffer_atomic_fmax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24725 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24726 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24729 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24730 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24735 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24736 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24739 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24740 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24745 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24746 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24749 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24750 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24753 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24754 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24757 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24758 { 276 /* buffer_atomic_fmin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24761 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24762 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24765 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24766 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24771 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24772 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24775 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24776 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24781 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24782 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24785 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24786 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24789 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24790 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24793 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24794 { 295 /* buffer_atomic_fmin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
77949 { 23715 /* v_mac_legacy_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
77950 { 23715 /* v_mac_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
77951 { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
78873 { 25163 /* v_mullit_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
78874 { 25163 /* v_mullit_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
78875 { 25163 /* v_mullit_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },