reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

11078   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11081   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11083   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11085   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11088   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11090   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11092   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11095   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11098   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11101   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11108   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11111   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11113   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11115   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11118   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11120   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11122   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11125   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11128   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11131   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11134   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11137   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11139   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11141   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11144   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11146   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11148   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11151   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11154   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11157   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11160   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11163   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11165   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11167   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11170   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11172   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11174   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11177   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11180   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11183   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11186   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11189   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11191   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11193   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11196   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11198   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11200   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11203   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11206   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11209   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11212   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11215   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11217   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11219   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11222   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11224   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11226   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11229   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11232   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11235   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11238   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11241   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11243   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11245   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11248   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11250   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11252   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11255   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11258   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11261   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11264   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11267   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11269   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11271   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11274   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11276   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11278   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11281   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11284   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11287   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11398   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11401   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11403   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11405   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11408   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11410   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11412   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11415   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11418   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11421   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11424   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11427   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11429   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11431   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11434   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11436   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11438   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11441   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11444   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11447   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11450   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11453   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11455   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11457   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11460   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11462   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11464   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11467   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11470   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11473   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11476   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11479   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11481   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11483   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11486   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11488   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11490   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11493   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11496   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11499   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11506   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11509   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11511   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11513   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11516   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11518   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11520   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11523   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11526   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11529   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11532   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11535   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11537   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11539   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11542   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11544   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11546   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11549   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11552   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11555   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11558   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11561   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11563   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11565   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11568   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11570   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11572   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11575   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11578   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11581   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11584   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11587   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11589   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11591   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11594   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11596   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11598   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11601   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11604   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11607   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11610   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11613   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11615   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11617   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11620   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11622   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11624   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11627   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11630   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11633   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11636   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11639   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11641   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11643   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11646   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11648   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11650   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11653   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11656   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11659   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11662   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11665   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11667   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11669   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11672   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11674   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11676   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11679   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11682   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11685   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11688   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11691   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11693   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11695   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11698   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11700   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11702   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11705   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11708   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11711   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11714   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11717   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11719   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11721   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11724   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11726   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11728   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11731   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11734   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11737   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11740   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11743   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11745   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11747   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11750   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11752   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11754   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11757   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11760   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11763   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11766   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11769   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11771   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11773   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11776   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11778   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11780   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11783   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11786   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11789   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11792   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11795   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11797   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11799   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11802   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11804   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11806   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11809   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11812   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11815   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11818   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11821   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11823   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11825   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11828   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11830   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11832   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11835   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11838   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11841   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11844   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11847   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11849   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11851   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11854   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11856   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11858   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11861   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11864   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11867   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11872   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11875   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11877   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11878   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11880   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11883   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11886   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11889   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11892   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11895   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11899   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11901   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11904   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11908   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11912   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11916   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11918   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11921   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11925   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11929   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11933   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11935   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11938   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11942   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11946   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12001   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12004   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12006   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12007   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12009   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12012   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12015   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12018   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12021   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12024   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12027   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12029   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12031   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12034   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12037   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12040   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12042   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12044   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12047   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12050   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12053   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12055   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12057   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12060   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12063   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12066   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12069   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12071   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12072   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12074   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12077   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12080   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12083   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12086   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12089   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12124   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12127   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12129   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12130   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12132   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12135   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12138   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12141   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12144   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12147   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12150   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12153   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12155   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12156   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12158   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12161   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12164   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12167   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12170   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12173   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12192   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12195   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12197   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12198   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12200   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12203   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12206   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12209   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12212   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12215   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12218   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12220   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12222   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12225   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12228   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12239   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12241   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12243   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12246   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12249   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12252   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12254   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12256   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12259   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12262   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12265   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12267   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12269   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12272   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12275   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12278   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12280   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12282   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12285   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12288   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12343   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12345   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12347   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12350   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12353   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12356   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12358   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12360   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12363   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12366   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12369   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12371   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12373   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12376   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12379   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12382   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12384   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12386   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12389   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12392   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12396   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12398   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12400   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12403   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12406   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12426   { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12429   { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12434   { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12437   { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12440   { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12443   { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12446   { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12449   { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12452   { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12455   { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12458   { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12461   { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12464   { 1936 /* ds_append */, AMDGPU::DS_APPEND_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12469   { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12472   { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12475   { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12478   { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12481   { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12484   { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12487   { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12490   { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12496   { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12499   { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12502   { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12505   { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12508   { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12511   { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12514   { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12517   { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12520   { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12523   { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12526   { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_ImmOffset, MCK_gds }, },
12532   { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_ImmOffset, MCK_gds }, },
12535   { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12538   { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12541   { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12544   { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12547   { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12550   { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12553   { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12556   { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12559   { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12562   { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12565   { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12568   { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12571   { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12574   { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12577   { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12580   { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12583   { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12586   { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12589   { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12592   { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12595   { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12598   { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12601   { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12604   { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12607   { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12610   { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12613   { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12616   { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12619   { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12622   { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12625   { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12628   { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12631   { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12634   { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12637   { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12640   { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12643   { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12646   { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12649   { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12652   { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12655   { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12658   { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12661   { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12664   { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12667   { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12670   { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12676   { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12679   { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12682   { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12685   { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12688   { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12691   { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12694   { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12699   { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12702   { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12705   { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12708   { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12716   { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12719   { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12725   { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12728   { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12735   { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12742   { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12749   { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12752   { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12755   { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12758   { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12761   { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12764   { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12767   { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12770   { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12773   { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12776   { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12779   { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12782   { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12785   { 3507 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
12791   { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12794   { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12797   { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12800   { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12808   { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12813   { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12816   { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12819   { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12827   { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12830   { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12833   { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12836   { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12839   { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12842   { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12845   { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12848   { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12851   { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12854   { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12857   { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12860   { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12863   { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12866   { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12869   { 3979 /* exp */, AMDGPU::EXP_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12872   { 3979 /* exp */, AMDGPU::EXP_DONE_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
17542   { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17545   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17548   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17551   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17554   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17557   { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_gfx6_gfx7, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
17560   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17563   { 7827 /* s_and_b64 */, AMDGPU::S_AND_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17567   { 7856 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
17576   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17579   { 7967 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17583   { 8000 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
17589   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17592   { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17812   { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17815   { 8531 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
17818   { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17821   { 8563 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
17824   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17827   { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17830   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17833   { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17836   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17839   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17848   { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17851   { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, },
17854   { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17857   { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, },
17862   { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17865   { 8794 /* s_brev_b64 */, AMDGPU::S_BREV_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18076   { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18078   { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18083   { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18085   { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18090   { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18092   { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18097   { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18099   { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18104   { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18106   { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18152   { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18155   { 9820 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18158   { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18175   { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18178   { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18181   { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18184   { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18187   { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18190   { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18193   { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18196   { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18199   { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18202   { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18205   { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18208   { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18212   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18215   { 10218 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18226   { 10269 /* s_dcache_inv */, AMDGPU::S_DCACHE_INV_si, Convert_NoOperands, AMFBS_isGFX6GFX7, {  }, },
18239   { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18242   { 10419 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18245   { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18248   { 10447 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18251   { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18254   { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18257   { 10489 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18260   { 10505 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18264   { 10547 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64 }, },
18267   { 10559 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_gfx6_gfx7, Convert__Reg1_0__ImmHwreg1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_ImmHwreg }, },
18274   { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18276   { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18281   { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18283   { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18288   { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18290   { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18295   { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18297   { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18302   { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18304   { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18317   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18320   { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18323   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18326   { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18329   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18332   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18337   { 10842 /* s_memtime */, AMDGPU::S_MEMTIME_si, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC }, },
18340   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18343   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18346   { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18349   { 10882 /* s_mov_b64 */, AMDGPU::S_MOV_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18352   { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18357   { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18360   { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18363   { 10947 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18366   { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18369   { 10975 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18377   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18380   { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_gfx6_gfx7, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18383   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18386   { 11064 /* s_nand_b64 */, AMDGPU::S_NAND_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18390   { 11095 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18394   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18397   { 11131 /* s_nor_b64 */, AMDGPU::S_NOR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18401   { 11160 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18404   { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18407   { 11189 /* s_not_b64 */, AMDGPU::S_NOT_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18410   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18413   { 11208 /* s_or_b64 */, AMDGPU::S_OR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18417   { 11235 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18423   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18426   { 11304 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18430   { 11335 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18439   { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18442   { 11424 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18445   { 11439 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64 }, },
18482   { 11733 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64 }, },
18486   { 11755 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_gfx6_gfx7, Convert__Reg1_1__ImmHwreg1_0, AMFBS_isGFX6GFX7, { MCK_ImmHwreg, MCK_SReg_32 }, },
18489   { 11768 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_gfx6_gfx7, Convert__Imm1_1__ImmHwreg1_0, AMFBS_isGFX6GFX7, { MCK_ImmHwreg, MCK_Imm }, },
18493   { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18496   { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18512   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18515   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18518   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18523   { 11956 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18538   { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18541   { 12141 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18544   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18547   { 12162 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18551   { 12193 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18554   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18557   { 12223 /* s_xor_b64 */, AMDGPU::S_XOR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18561   { 12252 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18700   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18702   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18704   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18707   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18710   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18713   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18715   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18717   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18720   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18723   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18726   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18728   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18730   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18733   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18736   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18739   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18741   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18743   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18746   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18749   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18800   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18802   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18804   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18807   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18810   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18813   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18815   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18817   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18820   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18823   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18826   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18828   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18830   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18833   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18836   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18839   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18841   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18843   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18846   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18849   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18860   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
18862   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18870   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18873   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18878   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18880   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18881   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18883   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
18888   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
18894   { 13631 /* v_clrexcp */, AMDGPU::V_CLREXCP_e32_gfx6_gfx7, Convert_NoOperands, AMFBS_isGFX6GFX7, {  }, },
18914   { 13693 /* v_cmp_class_f32_e32 */, AMDGPU::V_CMP_CLASS_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
18926   { 13729 /* v_cmp_class_f64_e32 */, AMDGPU::V_CMP_CLASS_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VGPR_32 }, },
18946   { 13792 /* v_cmp_eq_f32_e32 */, AMDGPU::V_CMP_EQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
18958   { 13822 /* v_cmp_eq_f64_e32 */, AMDGPU::V_CMP_EQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
18978   { 13882 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
18990   { 13912 /* v_cmp_eq_i64_e32 */, AMDGPU::V_CMP_EQ_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19010   { 13972 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19022   { 14002 /* v_cmp_eq_u64_e32 */, AMDGPU::V_CMP_EQ_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19042   { 14059 /* v_cmp_f_f32_e32 */, AMDGPU::V_CMP_F_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19054   { 14087 /* v_cmp_f_f64_e32 */, AMDGPU::V_CMP_F_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19070   { 14143 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19082   { 14171 /* v_cmp_f_i64_e32 */, AMDGPU::V_CMP_F_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19098   { 14227 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19110   { 14255 /* v_cmp_f_u64_e32 */, AMDGPU::V_CMP_F_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19130   { 14314 /* v_cmp_ge_f32_e32 */, AMDGPU::V_CMP_GE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19142   { 14344 /* v_cmp_ge_f64_e32 */, AMDGPU::V_CMP_GE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19162   { 14404 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19174   { 14434 /* v_cmp_ge_i64_e32 */, AMDGPU::V_CMP_GE_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19194   { 14494 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19206   { 14524 /* v_cmp_ge_u64_e32 */, AMDGPU::V_CMP_GE_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19226   { 14584 /* v_cmp_gt_f32_e32 */, AMDGPU::V_CMP_GT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19238   { 14614 /* v_cmp_gt_f64_e32 */, AMDGPU::V_CMP_GT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19258   { 14674 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19270   { 14704 /* v_cmp_gt_i64_e32 */, AMDGPU::V_CMP_GT_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19290   { 14764 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19302   { 14794 /* v_cmp_gt_u64_e32 */, AMDGPU::V_CMP_GT_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19322   { 14854 /* v_cmp_le_f32_e32 */, AMDGPU::V_CMP_LE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19334   { 14884 /* v_cmp_le_f64_e32 */, AMDGPU::V_CMP_LE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19354   { 14944 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19366   { 14974 /* v_cmp_le_i64_e32 */, AMDGPU::V_CMP_LE_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19386   { 15034 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19398   { 15064 /* v_cmp_le_u64_e32 */, AMDGPU::V_CMP_LE_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19418   { 15124 /* v_cmp_lg_f32_e32 */, AMDGPU::V_CMP_LG_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19430   { 15154 /* v_cmp_lg_f64_e32 */, AMDGPU::V_CMP_LG_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19450   { 15214 /* v_cmp_lt_f32_e32 */, AMDGPU::V_CMP_LT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19462   { 15244 /* v_cmp_lt_f64_e32 */, AMDGPU::V_CMP_LT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19482   { 15304 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19494   { 15334 /* v_cmp_lt_i64_e32 */, AMDGPU::V_CMP_LT_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19514   { 15394 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19526   { 15424 /* v_cmp_lt_u64_e32 */, AMDGPU::V_CMP_LT_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19546   { 15484 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19558   { 15514 /* v_cmp_ne_i64_e32 */, AMDGPU::V_CMP_NE_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19578   { 15574 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19590   { 15604 /* v_cmp_ne_u64_e32 */, AMDGPU::V_CMP_NE_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19610   { 15667 /* v_cmp_neq_f32_e32 */, AMDGPU::V_CMP_NEQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19622   { 15699 /* v_cmp_neq_f64_e32 */, AMDGPU::V_CMP_NEQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19642   { 15763 /* v_cmp_nge_f32_e32 */, AMDGPU::V_CMP_NGE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19654   { 15795 /* v_cmp_nge_f64_e32 */, AMDGPU::V_CMP_NGE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19674   { 15859 /* v_cmp_ngt_f32_e32 */, AMDGPU::V_CMP_NGT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19686   { 15891 /* v_cmp_ngt_f64_e32 */, AMDGPU::V_CMP_NGT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19706   { 15955 /* v_cmp_nle_f32_e32 */, AMDGPU::V_CMP_NLE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19718   { 15987 /* v_cmp_nle_f64_e32 */, AMDGPU::V_CMP_NLE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19738   { 16051 /* v_cmp_nlg_f32_e32 */, AMDGPU::V_CMP_NLG_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19750   { 16083 /* v_cmp_nlg_f64_e32 */, AMDGPU::V_CMP_NLG_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19770   { 16147 /* v_cmp_nlt_f32_e32 */, AMDGPU::V_CMP_NLT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19782   { 16179 /* v_cmp_nlt_f64_e32 */, AMDGPU::V_CMP_NLT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19802   { 16237 /* v_cmp_o_f32_e32 */, AMDGPU::V_CMP_O_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19814   { 16265 /* v_cmp_o_f64_e32 */, AMDGPU::V_CMP_O_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19830   { 16321 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19842   { 16349 /* v_cmp_t_i64_e32 */, AMDGPU::V_CMP_T_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19858   { 16405 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19870   { 16433 /* v_cmp_t_u64_e32 */, AMDGPU::V_CMP_T_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
19890   { 16495 /* v_cmp_tru_f32_e32 */, AMDGPU::V_CMP_TRU_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19902   { 16527 /* v_cmp_tru_f64_e32 */, AMDGPU::V_CMP_TRU_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
19922   { 16585 /* v_cmp_u_f32_e32 */, AMDGPU::V_CMP_U_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
19934   { 16613 /* v_cmp_u_f64_e32 */, AMDGPU::V_CMP_U_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20206   { 18828 /* v_cmpx_class_f32_e32 */, AMDGPU::V_CMPX_CLASS_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20216   { 18866 /* v_cmpx_class_f64_e32 */, AMDGPU::V_CMPX_CLASS_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VGPR_32 }, },
20232   { 18933 /* v_cmpx_eq_f32_e32 */, AMDGPU::V_CMPX_EQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20242   { 18965 /* v_cmpx_eq_f64_e32 */, AMDGPU::V_CMPX_EQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20258   { 19029 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20268   { 19061 /* v_cmpx_eq_i64_e32 */, AMDGPU::V_CMPX_EQ_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20284   { 19125 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20294   { 19157 /* v_cmpx_eq_u64_e32 */, AMDGPU::V_CMPX_EQ_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20310   { 19218 /* v_cmpx_f_f32_e32 */, AMDGPU::V_CMPX_F_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20320   { 19248 /* v_cmpx_f_f64_e32 */, AMDGPU::V_CMPX_F_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20334   { 19308 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20344   { 19338 /* v_cmpx_f_i64_e32 */, AMDGPU::V_CMPX_F_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20358   { 19398 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20368   { 19428 /* v_cmpx_f_u64_e32 */, AMDGPU::V_CMPX_F_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20384   { 19491 /* v_cmpx_ge_f32_e32 */, AMDGPU::V_CMPX_GE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20394   { 19523 /* v_cmpx_ge_f64_e32 */, AMDGPU::V_CMPX_GE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20410   { 19587 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20420   { 19619 /* v_cmpx_ge_i64_e32 */, AMDGPU::V_CMPX_GE_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20436   { 19683 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20446   { 19715 /* v_cmpx_ge_u64_e32 */, AMDGPU::V_CMPX_GE_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20462   { 19779 /* v_cmpx_gt_f32_e32 */, AMDGPU::V_CMPX_GT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20472   { 19811 /* v_cmpx_gt_f64_e32 */, AMDGPU::V_CMPX_GT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20488   { 19875 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20498   { 19907 /* v_cmpx_gt_i64_e32 */, AMDGPU::V_CMPX_GT_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20514   { 19971 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20524   { 20003 /* v_cmpx_gt_u64_e32 */, AMDGPU::V_CMPX_GT_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20540   { 20067 /* v_cmpx_le_f32_e32 */, AMDGPU::V_CMPX_LE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20550   { 20099 /* v_cmpx_le_f64_e32 */, AMDGPU::V_CMPX_LE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20566   { 20163 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20576   { 20195 /* v_cmpx_le_i64_e32 */, AMDGPU::V_CMPX_LE_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20592   { 20259 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20602   { 20291 /* v_cmpx_le_u64_e32 */, AMDGPU::V_CMPX_LE_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20618   { 20355 /* v_cmpx_lg_f32_e32 */, AMDGPU::V_CMPX_LG_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20628   { 20387 /* v_cmpx_lg_f64_e32 */, AMDGPU::V_CMPX_LG_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20644   { 20451 /* v_cmpx_lt_f32_e32 */, AMDGPU::V_CMPX_LT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20654   { 20483 /* v_cmpx_lt_f64_e32 */, AMDGPU::V_CMPX_LT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20670   { 20547 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20680   { 20579 /* v_cmpx_lt_i64_e32 */, AMDGPU::V_CMPX_LT_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20696   { 20643 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20706   { 20675 /* v_cmpx_lt_u64_e32 */, AMDGPU::V_CMPX_LT_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20722   { 20739 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20732   { 20771 /* v_cmpx_ne_i64_e32 */, AMDGPU::V_CMPX_NE_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20748   { 20835 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20758   { 20867 /* v_cmpx_ne_u64_e32 */, AMDGPU::V_CMPX_NE_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20774   { 20934 /* v_cmpx_neq_f32_e32 */, AMDGPU::V_CMPX_NEQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20784   { 20968 /* v_cmpx_neq_f64_e32 */, AMDGPU::V_CMPX_NEQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20800   { 21036 /* v_cmpx_nge_f32_e32 */, AMDGPU::V_CMPX_NGE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20810   { 21070 /* v_cmpx_nge_f64_e32 */, AMDGPU::V_CMPX_NGE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20826   { 21138 /* v_cmpx_ngt_f32_e32 */, AMDGPU::V_CMPX_NGT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20836   { 21172 /* v_cmpx_ngt_f64_e32 */, AMDGPU::V_CMPX_NGT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20852   { 21240 /* v_cmpx_nle_f32_e32 */, AMDGPU::V_CMPX_NLE_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20862   { 21274 /* v_cmpx_nle_f64_e32 */, AMDGPU::V_CMPX_NLE_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20878   { 21342 /* v_cmpx_nlg_f32_e32 */, AMDGPU::V_CMPX_NLG_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20888   { 21376 /* v_cmpx_nlg_f64_e32 */, AMDGPU::V_CMPX_NLG_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20904   { 21444 /* v_cmpx_nlt_f32_e32 */, AMDGPU::V_CMPX_NLT_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20914   { 21478 /* v_cmpx_nlt_f64_e32 */, AMDGPU::V_CMPX_NLT_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20930   { 21540 /* v_cmpx_o_f32_e32 */, AMDGPU::V_CMPX_O_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
20940   { 21570 /* v_cmpx_o_f64_e32 */, AMDGPU::V_CMPX_O_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
20954   { 21630 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20964   { 21660 /* v_cmpx_t_i64_e32 */, AMDGPU::V_CMPX_T_I64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
20978   { 21720 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20988   { 21750 /* v_cmpx_t_u64_e32 */, AMDGPU::V_CMPX_T_U64_e32_gfx6_gfx7, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB64, MCK_VReg_64 }, },
21004   { 21816 /* v_cmpx_tru_f32_e32 */, AMDGPU::V_CMPX_TRU_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
21014   { 21850 /* v_cmpx_tru_f64_e32 */, AMDGPU::V_CMPX_TRU_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
21030   { 21912 /* v_cmpx_u_f32_e32 */, AMDGPU::V_CMPX_U_F32_e32_gfx6_gfx7, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF32, MCK_VGPR_32 }, },
21040   { 21942 /* v_cmpx_u_f64_e32 */, AMDGPU::V_CMPX_U_F64_e32_gfx6_gfx7, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcF64, MCK_VReg_64 }, },
21043   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21054   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21057   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21064   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF16 }, },
21067   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21070   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21073   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21076   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21079   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21082   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21085   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21088   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF32 }, },
21091   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32 }, },
21094   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32 }, },
21097   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21102   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21105   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21112   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21114   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21115   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21116   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21117   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21118   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21120   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21122   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21127   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21130   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21141   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21146   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21149   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21152   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21157   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21172   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21175   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21180   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21183   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21188   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21191   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21194   { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_si, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
21197   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_si, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21200   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_si, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21203   { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_si, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21207   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21212   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21219   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21224   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21228   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21234   { 23982 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_gfx6_gfx7, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, },
21238   { 24006 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_gfx6_gfx7, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, },
21243   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21247   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21252   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21254   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21255   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21259   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21263   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21268   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21271   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21274   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21289   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21292   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21295   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21298   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21301   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21305   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21308   { 25176 /* v_nop */, AMDGPU::V_NOP_e32_gfx6_gfx7, Convert_NoOperands, AMFBS_isGFX6GFX7, {  }, },
21311   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21314   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21324   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21327   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21330   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21335   { 25692 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_gfx6_gfx7, Convert__Reg1_0__Reg1_1__SCSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_VRegOrLds_32, MCK_SCSrcB32 }, },
21340   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21350   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21353   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21362   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21367   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21370   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21381   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21383   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21391   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21396   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21407   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21409   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21420   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21426   { 26350 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_gfx6_gfx7, Convert__Reg1_0__SSrcOrLdsB321_1__SCSrcB321_2__Tie0_1_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_SSrcOrLdsB32, MCK_SCSrcB32 }, },
21431   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21450   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21453   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21457   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21470   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21473   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21476   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21479   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21488   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21493   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21496   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21499   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21502   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21505   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21508   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21513   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21519   { 13631 /* v_clrexcp */, AMDGPU::V_CLREXCP_e64_gfx6_gfx7, Convert_NoOperands, AMFBS_isGFX6GFX7, {  }, },
21524   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21527   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21532   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21535   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21540   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21543   { 13899 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21548   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21551   { 13989 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21556   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21559   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21563   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21566   { 14159 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21570   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21573   { 14243 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21578   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21581   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21586   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21589   { 14421 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21594   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21597   { 14511 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21602   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21605   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21610   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21613   { 14691 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21618   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21621   { 14781 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21626   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21629   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21634   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21637   { 14961 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21642   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21645   { 15051 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21650   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21653   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21658   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21661   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21666   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21669   { 15321 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21674   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21677   { 15411 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21682   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21685   { 15501 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21690   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21693   { 15591 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21698   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21701   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21706   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21709   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21714   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21717   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21722   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21725   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21730   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21733   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21738   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21741   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21746   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21749   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21753   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21756   { 16337 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21760   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21763   { 16421 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21768   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21771   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21776   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21779   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21848   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21851   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21856   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21859   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21864   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21867   { 19047 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21872   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21875   { 19143 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21880   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21883   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21887   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21890   { 19325 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21894   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21897   { 19415 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21902   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21905   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21910   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21913   { 19605 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21918   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21921   { 19701 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21926   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21929   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21934   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21937   { 19893 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21942   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21945   { 19989 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21950   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21953   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21958   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21961   { 20181 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21966   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21969   { 20277 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21974   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21977   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21982   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21985   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21990   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21993   { 20565 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21998   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22001   { 20661 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22006   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22009   { 20757 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22014   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22017   { 20853 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22022   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22025   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22030   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22033   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22038   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22041   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22046   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22049   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22054   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22057   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22062   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22065   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22070   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22073   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22077   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22080   { 21647 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22084   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22087   { 21737 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
22092   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22095   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22100   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22103   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22106   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_BoolReg }, },
22117   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22120   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22123   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22126   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22129   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22132   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22139   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22142   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22145   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22148   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22151   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22154   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22157   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22160   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22163   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22166   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22169   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22172   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22177   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22180   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22187   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22190   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22193   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22196   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22199   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22205   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22211   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22215   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22218   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22223   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22226   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22232   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22235   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22239   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22242   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22245   { 22704 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_gfx6_gfx7, Convert__Reg1_0__BoolReg1_1__VSrcF321_2__VSrcF321_3__VSrcF321_4, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcF32, MCK_VSrcF32, MCK_VSrcF32 }, },
22248   { 22720 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_gfx6_gfx7, Convert__Reg1_0__BoolReg1_1__VSrcF641_2__VSrcF641_3__VSrcF641_4, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcF64, MCK_VSrcF64, MCK_VSrcF64 }, },
22267   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22272   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22275   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22278   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22283   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22292   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22295   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22310   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22313   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22318   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22321   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22326   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22329   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22349   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22352   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22355   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22361   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22374   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22383   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22389   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22396   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22404   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22411   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22424   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22432   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22437   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22442   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22447   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22450   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22455   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22461   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22464   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22467   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22472   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22477   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22482   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22507   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22512   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22517   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22522   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22525   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22530   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22536   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22539   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22542   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22555   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22561   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22566   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22569   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22572   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22575   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22578   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22581   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22584   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22587   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22590   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22595   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22598   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22603   { 25176 /* v_nop */, AMDGPU::V_NOP_e64_gfx6_gfx7, Convert_NoOperands, AMFBS_isGFX6GFX7, {  }, },
22606   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22611   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22666   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22669   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22672   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22678   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22688   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22691   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22695   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22698   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22701   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22704   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22712   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22717   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22720   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22732   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22736   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22747   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22752   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22764   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22766   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22772   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22777   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22788   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
24159   { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24160   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24165   { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24166   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24169   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24170   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24173   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24174   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24179   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24180   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24183   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24184   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24187   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24188   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24193   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24194   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24199   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24200   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24205   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24206   { 0 /* buffer_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24219   { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24220   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24225   { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24226   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24229   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24230   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24233   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24234   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24239   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24240   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24243   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24244   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24247   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24248   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24253   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24254   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24259   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24260   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24265   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24266   { 40 /* buffer_atomic_add_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24271   { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24272   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24277   { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24278   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24281   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24282   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24285   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24286   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24291   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24292   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24295   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24296   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24299   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24300   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24305   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24306   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24311   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24312   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24317   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24318   { 61 /* buffer_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24323   { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24324   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24329   { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24330   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24333   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24334   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24337   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24338   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24343   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24344   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24347   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24348   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24351   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24352   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24357   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24358   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24363   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24364   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24369   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24370   { 79 /* buffer_atomic_and_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24375   { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24376   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24381   { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24382   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24385   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24386   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24389   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24390   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24395   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24396   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24399   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24400   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24403   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24404   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24409   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24410   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24415   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24416   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24421   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24422   { 100 /* buffer_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24427   { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24428   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24433   { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24434   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24437   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24438   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24441   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24442   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24447   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24448   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24451   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24452   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24455   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24456   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24461   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24462   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24467   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24468   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24473   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24474   { 122 /* buffer_atomic_cmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24479   { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24480   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24485   { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24486   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24489   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24490   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24493   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24494   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24499   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24500   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24503   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24504   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24507   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24508   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24513   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24514   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24519   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24520   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24525   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24526   { 147 /* buffer_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24531   { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24532   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24537   { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24538   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24541   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24542   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24545   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24546   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24551   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24552   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24555   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24556   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24559   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24560   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24565   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24566   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24571   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24572   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24577   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24578   { 165 /* buffer_atomic_dec_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24799   { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24800   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24805   { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24806   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24809   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24810   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24813   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24814   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24819   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24820   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24823   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24824   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24827   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24828   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24833   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24834   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24839   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24840   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24845   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24846   { 317 /* buffer_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24851   { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24852   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24857   { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24858   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24861   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24862   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24865   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24866   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24871   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24872   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24875   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24876   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24879   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24880   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24885   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24886   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24891   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24892   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24897   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24898   { 335 /* buffer_atomic_inc_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24903   { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24904   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24909   { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24910   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24913   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24914   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24917   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24918   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24923   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24924   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24927   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24928   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24931   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24932   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24937   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24938   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24943   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24944   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24949   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24950   { 356 /* buffer_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24955   { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24956   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24961   { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24962   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24965   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24966   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24969   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24970   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24975   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24976   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24979   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24980   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24983   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24984   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24989   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24990   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24995   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24996   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25001   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25002   { 373 /* buffer_atomic_or_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25015   { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25016   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25021   { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25022   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25025   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25026   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25029   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25030   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25035   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25036   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25039   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25040   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25043   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25044   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25049   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25050   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25055   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25056   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25061   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25062   { 418 /* buffer_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25067   { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25068   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25073   { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25074   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25077   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25078   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25081   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25082   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25087   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25088   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25091   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25092   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25095   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25096   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25101   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25102   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25107   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25108   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25113   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25114   { 437 /* buffer_atomic_smax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25119   { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25120   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25125   { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25126   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25129   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25130   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25133   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25134   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25139   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25140   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25143   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25144   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25147   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25148   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25153   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25154   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25159   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25160   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25165   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25166   { 459 /* buffer_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25171   { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25172   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25177   { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25178   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25181   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25182   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25185   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25186   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25191   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25192   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25195   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25196   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25199   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25200   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25205   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25206   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25211   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25212   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25217   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25218   { 478 /* buffer_atomic_smin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25223   { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25224   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25229   { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25230   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25233   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25234   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25237   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25238   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25243   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25244   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25247   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25248   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25251   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25252   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25257   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25258   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25263   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25264   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25269   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25270   { 500 /* buffer_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25275   { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25276   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25281   { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25282   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25285   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25286   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25289   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25290   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25295   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25296   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25299   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25300   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25303   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25304   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25309   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25310   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25315   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25316   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25321   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25322   { 518 /* buffer_atomic_sub_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25327   { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25328   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25333   { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25334   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25337   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25338   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25341   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25342   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25347   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25348   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25351   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25352   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25355   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25356   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25361   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25362   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25367   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25368   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25373   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25374   { 539 /* buffer_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25379   { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25380   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25385   { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25386   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25389   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25390   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25393   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25394   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25399   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25400   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25403   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25404   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25407   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25408   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25413   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25414   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25419   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25420   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25425   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25426   { 558 /* buffer_atomic_swap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25431   { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25432   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25437   { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25438   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25441   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25442   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25445   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25446   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25451   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25452   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25455   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25456   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25459   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25460   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25465   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25466   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25471   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25472   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25477   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25478   { 580 /* buffer_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25483   { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25484   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25489   { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25490   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25493   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25494   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25497   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25498   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25503   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25504   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25507   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25508   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25511   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25512   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25517   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25518   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25523   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25524   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25529   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25530   { 599 /* buffer_atomic_umax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25535   { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25536   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25541   { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25542   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25545   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25546   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25549   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25550   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25555   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25556   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25559   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25560   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25563   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25564   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25569   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25570   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25575   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25576   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25581   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25582   { 621 /* buffer_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25587   { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25588   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25593   { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25594   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25597   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25598   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25601   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25602   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25607   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25608   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25611   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25612   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25615   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25616   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25621   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25622   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25627   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25628   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25633   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25634   { 640 /* buffer_atomic_umin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25639   { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25640   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25645   { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25646   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25649   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25650   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25653   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25654   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25659   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25660   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25663   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25664   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25667   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25668   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25673   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25674   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25679   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25680   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25685   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25686   { 662 /* buffer_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25691   { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25692   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25697   { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25698   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25701   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25702   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25705   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25706   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25711   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25712   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25715   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25716   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25719   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25720   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25725   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25726   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25731   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25732   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25737   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25738   { 680 /* buffer_atomic_xor_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25746   { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25747   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25748   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25749   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25750   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25762   { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25763   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25764   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25765   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25766   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25767   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25774   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25775   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25776   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25777   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25778   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25779   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25780   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25781   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25782   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25783   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25784   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25790   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25791   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25792   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25793   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25794   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25806   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25807   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25808   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25809   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25810   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25811   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25823   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25824   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25825   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25826   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25827   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25839   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25840   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25841   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25842   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25843   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25844   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25856   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25857   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25858   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25859   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25860   { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25872   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25873   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25874   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25875   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25876   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25877   { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25895   { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25896   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25897   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25898   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25899   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25900   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25907   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25908   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25909   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25910   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25911   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25912   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25924   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25925   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25926   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25927   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25928   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25929   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25947   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25948   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25949   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25950   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25951   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25952   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25970   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25971   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25972   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25973   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25974   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25975   { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25993   { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25994   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
25995   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25996   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25997   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
25998   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26005   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26006   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26007   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26008   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26009   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26010   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26022   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26023   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26024   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26025   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26026   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26027   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26045   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26046   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26047   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26048   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26049   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26050   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26068   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26069   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26070   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26071   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26072   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26073   { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26091   { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26092   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26093   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26094   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26095   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26096   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26103   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26104   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26105   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26106   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26107   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26108   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26120   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26121   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26122   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26123   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26124   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26125   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26143   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26144   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26145   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26146   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26147   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26148   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26166   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26167   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26168   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26169   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26170   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26171   { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26495   { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26496   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26497   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26498   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26499   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26511   { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26512   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26513   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26514   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26515   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26516   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26523   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26524   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26525   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26526   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26527   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26528   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26529   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26530   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26531   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26532   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26533   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26539   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26540   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26541   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26542   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26543   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26555   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26556   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26557   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26558   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26559   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26560   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26572   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26573   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26574   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26575   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26576   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26588   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26589   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26590   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26591   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26592   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26593   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26605   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26606   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26607   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26608   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26609   { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26621   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26622   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26623   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26624   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26625   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26626   { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26639   { 964 /* buffer_load_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26640   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26641   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26642   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26643   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26644   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26651   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26652   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26653   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26654   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26655   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26656   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26663   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26664   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26665   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26666   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26667   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26668   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26681   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26682   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26683   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26684   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26685   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26686   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26699   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26700   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26701   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26702   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26703   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26704   { 964 /* buffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26717   { 986 /* buffer_load_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26718   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26719   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26720   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26721   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26722   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26729   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26730   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26731   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26732   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26733   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26734   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26741   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26742   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26743   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26744   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26745   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26746   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26759   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26760   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26761   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26762   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26763   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26764   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26777   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26778   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26779   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26780   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26781   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26782   { 986 /* buffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26795   { 1009 /* buffer_load_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26796   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26797   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26798   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26799   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26800   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26807   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26808   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26809   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26810   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26811   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26812   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26819   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26820   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26821   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26822   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26823   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26824   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26837   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26838   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26839   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26840   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26841   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26842   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26855   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26856   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26857   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26858   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26859   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26860   { 1009 /* buffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26872   { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26873   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26874   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26875   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26876   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26888   { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26889   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26890   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26891   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26892   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26893   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26900   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26901   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26902   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26903   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26904   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26905   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26906   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26907   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26908   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26909   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26910   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26916   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26917   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26918   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26919   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26920   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26932   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26933   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26934   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26935   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26936   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26937   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26949   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26950   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26951   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26952   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26953   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26965   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26966   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26967   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26968   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26969   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
26970   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26982   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26983   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
26984   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26985   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26986   { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26998   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26999   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27000   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27001   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27002   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27003   { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27207   { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27208   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27209   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27210   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27211   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27223   { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27224   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27225   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27226   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27227   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27228   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27235   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27236   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27237   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27238   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27239   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27240   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27241   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27242   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27243   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27244   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27245   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27251   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27252   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27253   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27254   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27255   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27267   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27268   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27269   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27270   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27271   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27272   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27284   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27285   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27286   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27287   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27288   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27300   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27301   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27302   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27303   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27304   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27305   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27317   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27318   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27319   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27320   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27321   { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27333   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27334   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27335   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27336   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27337   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27338   { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27350   { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27351   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27352   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27353   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27354   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27366   { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27367   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27368   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27369   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27370   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27371   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27378   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27379   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27380   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27381   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27382   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27383   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27384   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27385   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27386   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27387   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27388   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27394   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27395   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27396   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27397   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27398   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27410   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27411   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27412   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27413   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27414   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27415   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27427   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27428   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27429   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27430   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27431   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27443   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27444   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27445   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27446   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27447   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27448   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27460   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27461   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27462   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27463   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27464   { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27476   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27477   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27478   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27479   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27480   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27481   { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27589   { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27590   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27591   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27592   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27593   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27605   { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27606   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27607   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27608   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27609   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27610   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27617   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27618   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27619   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27620   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27621   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27622   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27623   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27624   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27625   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27626   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27627   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27633   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27634   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27635   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27636   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27637   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27649   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27650   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27651   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27652   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27653   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27654   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27666   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27667   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27668   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27669   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27670   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27682   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27683   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27684   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27685   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27686   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27687   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27699   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27700   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27701   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27702   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27703   { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27715   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27716   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27717   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27718   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27719   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27720   { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27733   { 1248 /* buffer_store_byte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27734   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27735   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27736   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27737   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27738   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27745   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27746   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27747   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27748   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27749   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27750   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27757   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27758   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27759   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27760   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27761   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27762   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27775   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27776   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27777   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27778   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27779   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27780   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27793   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27794   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27795   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27796   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27797   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27798   { 1248 /* buffer_store_byte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27859   { 1291 /* buffer_store_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27860   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27861   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27862   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27863   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27864   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27871   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27872   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27873   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27874   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27875   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27876   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27883   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27884   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27885   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27886   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27887   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27888   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27901   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27902   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27903   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27904   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27905   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27906   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27919   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27920   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27921   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27922   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27923   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27924   { 1291 /* buffer_store_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27937   { 1310 /* buffer_store_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27938   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27939   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27940   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27941   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27942   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27949   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27950   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27951   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27952   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27953   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27954   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27961   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27962   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27963   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27964   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27965   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27966   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27979   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27980   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27981   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27982   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27983   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
27984   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27997   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27998   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
27999   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28000   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28001   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28002   { 1310 /* buffer_store_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28015   { 1331 /* buffer_store_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28016   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28017   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28018   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28019   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28020   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28027   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28028   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28029   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28030   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28031   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28032   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28039   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28040   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28041   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28042   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28043   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28044   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28057   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28058   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28059   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28060   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28061   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28062   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28075   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28076   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28077   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28078   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28079   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28080   { 1331 /* buffer_store_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28093   { 1352 /* buffer_store_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28094   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28095   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28096   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28097   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28098   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28105   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28106   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28107   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28108   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28109   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28110   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28117   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28118   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28119   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28120   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28121   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28122   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28135   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28136   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28137   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28138   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28139   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28140   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28153   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28154   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28155   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28156   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28157   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28158   { 1352 /* buffer_store_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28483   { 1512 /* buffer_store_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28484   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28485   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28486   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28487   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28488   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28495   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28496   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28497   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28498   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28499   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28500   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28507   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28508   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28509   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28510   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28511   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28512   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28525   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28526   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28527   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28528   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28529   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28530   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28543   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28544   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28545   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28546   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28547   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28548   { 1512 /* buffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28561   { 1534 /* buffer_store_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28562   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28563   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28564   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28565   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28566   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28573   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28574   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28575   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28576   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28577   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28578   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28585   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28586   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28587   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28588   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28589   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28590   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28603   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28604   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28605   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28606   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28607   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28608   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28621   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28622   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28623   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28624   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28625   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28626   { 1534 /* buffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28639   { 1557 /* buffer_store_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28640   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28641   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28642   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28643   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28644   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28651   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28652   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28653   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28654   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28655   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28656   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28663   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28664   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28665   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28666   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28667   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28668   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28681   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28682   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28683   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28684   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28685   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28686   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28699   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28700   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28701   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28702   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28703   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28704   { 1557 /* buffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28717   { 1581 /* buffer_store_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28718   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28719   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28720   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28721   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28722   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28729   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28730   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28731   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28732   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28733   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28734   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28741   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28742   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28743   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28744   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28745   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28746   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28759   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28760   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28761   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28762   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28763   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28764   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28777   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28778   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28779   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28780   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28781   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28782   { 1581 /* buffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28799   { 1629 /* buffer_store_short */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28800   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28801   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28802   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28803   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28804   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28811   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28812   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28813   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28814   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28815   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28816   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28823   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28824   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28825   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28826   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28827   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28828   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28841   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28842   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28843   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28844   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28845   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28846   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28859   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28860   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
28861   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28862   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28863   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
28864   { 1629 /* buffer_store_short */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28929   { 1752 /* ds_add_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28930   { 1752 /* ds_add_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28935   { 1767 /* ds_add_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28936   { 1767 /* ds_add_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28945   { 1798 /* ds_add_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28946   { 1798 /* ds_add_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28951   { 1814 /* ds_add_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28952   { 1814 /* ds_add_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28957   { 1830 /* ds_add_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28958   { 1830 /* ds_add_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28963   { 1841 /* ds_add_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28964   { 1841 /* ds_add_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28969   { 1852 /* ds_and_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28970   { 1852 /* ds_and_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28975   { 1863 /* ds_and_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28976   { 1863 /* ds_and_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28981   { 1874 /* ds_and_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28982   { 1874 /* ds_and_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28987   { 1889 /* ds_and_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28988   { 1889 /* ds_and_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28993   { 1904 /* ds_and_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28994   { 1904 /* ds_and_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
28999   { 1920 /* ds_and_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29000   { 1920 /* ds_and_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29005   { 1936 /* ds_append */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29006   { 1936 /* ds_append */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29013   { 1962 /* ds_cmpst_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29014   { 1962 /* ds_cmpst_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29019   { 1975 /* ds_cmpst_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29020   { 1975 /* ds_cmpst_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29025   { 1988 /* ds_cmpst_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29026   { 1988 /* ds_cmpst_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29031   { 2001 /* ds_cmpst_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29032   { 2001 /* ds_cmpst_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29037   { 2014 /* ds_cmpst_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29038   { 2014 /* ds_cmpst_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29043   { 2031 /* ds_cmpst_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29044   { 2031 /* ds_cmpst_rtn_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29049   { 2048 /* ds_cmpst_rtn_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29050   { 2048 /* ds_cmpst_rtn_f32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29055   { 2065 /* ds_cmpst_rtn_f64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29056   { 2065 /* ds_cmpst_rtn_f64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29067   { 2104 /* ds_consume */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29068   { 2104 /* ds_consume */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29073   { 2115 /* ds_dec_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29074   { 2115 /* ds_dec_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29079   { 2130 /* ds_dec_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29080   { 2130 /* ds_dec_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29085   { 2145 /* ds_dec_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29086   { 2145 /* ds_dec_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29091   { 2161 /* ds_dec_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29092   { 2161 /* ds_dec_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29097   { 2177 /* ds_dec_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29098   { 2177 /* ds_dec_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29103   { 2188 /* ds_dec_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29104   { 2188 /* ds_dec_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29108   { 2199 /* ds_gws_barrier */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29111   { 2214 /* ds_gws_init */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29114   { 2226 /* ds_gws_sema_br */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29117   { 2241 /* ds_gws_sema_p */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29123   { 2279 /* ds_gws_sema_v */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29127   { 2293 /* ds_inc_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29128   { 2293 /* ds_inc_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29133   { 2308 /* ds_inc_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29134   { 2308 /* ds_inc_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29139   { 2323 /* ds_inc_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29140   { 2323 /* ds_inc_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29145   { 2339 /* ds_inc_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29146   { 2339 /* ds_inc_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29151   { 2355 /* ds_inc_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29152   { 2355 /* ds_inc_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29157   { 2366 /* ds_inc_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29158   { 2366 /* ds_inc_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29163   { 2377 /* ds_max_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29164   { 2377 /* ds_max_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29169   { 2388 /* ds_max_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29170   { 2388 /* ds_max_f64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29175   { 2399 /* ds_max_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29176   { 2399 /* ds_max_i32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29181   { 2410 /* ds_max_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29182   { 2410 /* ds_max_i64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29187   { 2421 /* ds_max_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29188   { 2421 /* ds_max_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29193   { 2436 /* ds_max_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29194   { 2436 /* ds_max_rtn_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29199   { 2451 /* ds_max_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29200   { 2451 /* ds_max_rtn_i32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29205   { 2466 /* ds_max_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29206   { 2466 /* ds_max_rtn_i64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29211   { 2481 /* ds_max_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29212   { 2481 /* ds_max_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29217   { 2496 /* ds_max_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29218   { 2496 /* ds_max_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29223   { 2511 /* ds_max_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29224   { 2511 /* ds_max_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29229   { 2527 /* ds_max_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29230   { 2527 /* ds_max_src2_f64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29235   { 2543 /* ds_max_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29236   { 2543 /* ds_max_src2_i32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29241   { 2559 /* ds_max_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29242   { 2559 /* ds_max_src2_i64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29247   { 2575 /* ds_max_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29248   { 2575 /* ds_max_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29253   { 2591 /* ds_max_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29254   { 2591 /* ds_max_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29259   { 2607 /* ds_max_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29260   { 2607 /* ds_max_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29265   { 2618 /* ds_max_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29266   { 2618 /* ds_max_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29271   { 2629 /* ds_min_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29272   { 2629 /* ds_min_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29277   { 2640 /* ds_min_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29278   { 2640 /* ds_min_f64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29283   { 2651 /* ds_min_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29284   { 2651 /* ds_min_i32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29289   { 2662 /* ds_min_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29290   { 2662 /* ds_min_i64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29295   { 2673 /* ds_min_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29296   { 2673 /* ds_min_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29301   { 2688 /* ds_min_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29302   { 2688 /* ds_min_rtn_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29307   { 2703 /* ds_min_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29308   { 2703 /* ds_min_rtn_i32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29313   { 2718 /* ds_min_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29314   { 2718 /* ds_min_rtn_i64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29319   { 2733 /* ds_min_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29320   { 2733 /* ds_min_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29325   { 2748 /* ds_min_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29326   { 2748 /* ds_min_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29331   { 2763 /* ds_min_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29332   { 2763 /* ds_min_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29337   { 2779 /* ds_min_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29338   { 2779 /* ds_min_src2_f64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29343   { 2795 /* ds_min_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29344   { 2795 /* ds_min_src2_i32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29349   { 2811 /* ds_min_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29350   { 2811 /* ds_min_src2_i64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29355   { 2827 /* ds_min_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29356   { 2827 /* ds_min_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29361   { 2843 /* ds_min_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29362   { 2843 /* ds_min_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29367   { 2859 /* ds_min_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29368   { 2859 /* ds_min_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29373   { 2870 /* ds_min_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29374   { 2870 /* ds_min_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29379   { 2881 /* ds_mskor_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29380   { 2881 /* ds_mskor_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29385   { 2894 /* ds_mskor_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29386   { 2894 /* ds_mskor_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29391   { 2907 /* ds_mskor_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29392   { 2907 /* ds_mskor_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29397   { 2924 /* ds_mskor_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29398   { 2924 /* ds_mskor_rtn_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29403   { 2948 /* ds_or_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29404   { 2948 /* ds_or_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29409   { 2958 /* ds_or_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29410   { 2958 /* ds_or_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29415   { 2968 /* ds_or_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29416   { 2968 /* ds_or_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29421   { 2982 /* ds_or_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29422   { 2982 /* ds_or_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29427   { 2996 /* ds_or_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29428   { 2996 /* ds_or_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29433   { 3011 /* ds_or_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29434   { 3011 /* ds_or_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29438   { 3026 /* ds_ordered_count */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29445   { 3058 /* ds_read2_b32 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29446   { 3058 /* ds_read2_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29447   { 3058 /* ds_read2_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29454   { 3071 /* ds_read2_b64 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29455   { 3071 /* ds_read2_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29456   { 3071 /* ds_read2_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29463   { 3084 /* ds_read2st64_b32 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29464   { 3084 /* ds_read2st64_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29465   { 3084 /* ds_read2st64_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29472   { 3101 /* ds_read2st64_b64 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29473   { 3101 /* ds_read2st64_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29474   { 3101 /* ds_read2st64_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29490   { 3150 /* ds_read_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29491   { 3150 /* ds_read_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29496   { 3162 /* ds_read_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29497   { 3162 /* ds_read_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29508   { 3186 /* ds_read_i16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29509   { 3186 /* ds_read_i16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29514   { 3198 /* ds_read_i8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29515   { 3198 /* ds_read_i8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29528   { 3242 /* ds_read_u16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29529   { 3242 /* ds_read_u16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29542   { 3289 /* ds_read_u8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29543   { 3289 /* ds_read_u8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29556   { 3333 /* ds_rsub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29557   { 3333 /* ds_rsub_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29562   { 3349 /* ds_rsub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29563   { 3349 /* ds_rsub_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29568   { 3365 /* ds_rsub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29569   { 3365 /* ds_rsub_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29574   { 3382 /* ds_rsub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29575   { 3382 /* ds_rsub_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29580   { 3399 /* ds_rsub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29581   { 3399 /* ds_rsub_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29586   { 3411 /* ds_rsub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29587   { 3411 /* ds_rsub_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29592   { 3423 /* ds_sub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29593   { 3423 /* ds_sub_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29598   { 3438 /* ds_sub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29599   { 3438 /* ds_sub_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29604   { 3453 /* ds_sub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29605   { 3453 /* ds_sub_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29610   { 3469 /* ds_sub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29611   { 3469 /* ds_sub_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29616   { 3485 /* ds_sub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29617   { 3485 /* ds_sub_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29622   { 3496 /* ds_sub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29623   { 3496 /* ds_sub_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29628   { 3507 /* ds_swizzle_b32 */, 4 /* 2 */, MCK_Swizzle, AMFBS_isGFX6GFX7 },
29629   { 3507 /* ds_swizzle_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29641   { 3538 /* ds_write2_b32 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29642   { 3538 /* ds_write2_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29643   { 3538 /* ds_write2_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29650   { 3552 /* ds_write2_b64 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29651   { 3552 /* ds_write2_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29652   { 3552 /* ds_write2_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29659   { 3566 /* ds_write2st64_b32 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29660   { 3566 /* ds_write2st64_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29661   { 3566 /* ds_write2st64_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29668   { 3584 /* ds_write2st64_b64 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29669   { 3584 /* ds_write2st64_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29670   { 3584 /* ds_write2st64_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29686   { 3636 /* ds_write_b16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29687   { 3636 /* ds_write_b16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29696   { 3669 /* ds_write_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29697   { 3669 /* ds_write_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29702   { 3682 /* ds_write_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29703   { 3682 /* ds_write_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29708   { 3695 /* ds_write_b8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29709   { 3695 /* ds_write_b8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29724   { 3739 /* ds_write_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29725   { 3739 /* ds_write_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29730   { 3757 /* ds_write_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29731   { 3757 /* ds_write_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29737   { 3775 /* ds_wrxchg2_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29738   { 3775 /* ds_wrxchg2_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29739   { 3775 /* ds_wrxchg2_rtn_b32 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29746   { 3794 /* ds_wrxchg2_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29747   { 3794 /* ds_wrxchg2_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29748   { 3794 /* ds_wrxchg2_rtn_b64 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29755   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29756   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29757   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29764   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX6GFX7 },
29765   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29766   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29772   { 3859 /* ds_wrxchg_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29773   { 3859 /* ds_wrxchg_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29778   { 3877 /* ds_wrxchg_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29779   { 3877 /* ds_wrxchg_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29784   { 3895 /* ds_xor_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29785   { 3895 /* ds_xor_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29790   { 3906 /* ds_xor_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29791   { 3906 /* ds_xor_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29796   { 3917 /* ds_xor_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29797   { 3917 /* ds_xor_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29802   { 3932 /* ds_xor_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29803   { 3932 /* ds_xor_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29808   { 3947 /* ds_xor_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29809   { 3947 /* ds_xor_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29814   { 3963 /* ds_xor_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29815   { 3963 /* ds_xor_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX6GFX7 },
29822   { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX6GFX7 },
29823   { 3979 /* exp */, 32 /* 5 */, MCK_ImmExpCompr, AMFBS_isGFX6GFX7 },
29824   { 3979 /* exp */, 64 /* 6 */, MCK_ImmExpVM, AMFBS_isGFX6GFX7 },
29825   { 3979 /* exp */, 1 /* 0 */, MCK_ImmExpTgt, AMFBS_isGFX6GFX7 },
29834   { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX6GFX7 },
29835   { 3979 /* exp */, 64 /* 6 */, MCK_ImmExpCompr, AMFBS_isGFX6GFX7 },
29836   { 3979 /* exp */, 128 /* 7 */, MCK_ImmExpVM, AMFBS_isGFX6GFX7 },
29837   { 3979 /* exp */, 1 /* 0 */, MCK_ImmExpTgt, AMFBS_isGFX6GFX7 },
70753   { 9380 /* s_buffer_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70754   { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70757   { 9380 /* s_buffer_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70758   { 9380 /* s_buffer_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70759   { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70771   { 9400 /* s_buffer_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70772   { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70775   { 9400 /* s_buffer_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70776   { 9400 /* s_buffer_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70777   { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70789   { 9423 /* s_buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70790   { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70793   { 9423 /* s_buffer_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70794   { 9423 /* s_buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70795   { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70807   { 9445 /* s_buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70808   { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70811   { 9445 /* s_buffer_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70812   { 9445 /* s_buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70813   { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70825   { 9467 /* s_buffer_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70826   { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70829   { 9467 /* s_buffer_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70830   { 9467 /* s_buffer_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70831   { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70901   { 10559 /* s_getreg_b32 */, 2 /* 1 */, MCK_ImmHwreg, AMFBS_isGFX6GFX7 },
70905   { 10626 /* s_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70906   { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70909   { 10626 /* s_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70910   { 10626 /* s_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70911   { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70923   { 10639 /* s_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70924   { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70927   { 10639 /* s_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70928   { 10639 /* s_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70929   { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70941   { 10655 /* s_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70942   { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70945   { 10655 /* s_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70946   { 10655 /* s_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70947   { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70959   { 10670 /* s_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70960   { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70963   { 10670 /* s_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70964   { 10670 /* s_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70965   { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70977   { 10685 /* s_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70978   { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70981   { 10685 /* s_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 },
70982   { 10685 /* s_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
70983   { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71058   { 11755 /* s_setreg_b32 */, 1 /* 0 */, MCK_ImmHwreg, AMFBS_isGFX6GFX7 },
71061   { 11768 /* s_setreg_imm32_b32 */, 1 /* 0 */, MCK_ImmHwreg, AMFBS_isGFX6GFX7 },
71791   { 12866 /* tbuffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71792   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71793   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71794   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71795   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71796   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71797   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71805   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71806   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71807   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71808   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71809   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71810   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71811   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71819   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71820   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71821   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71822   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71823   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71824   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71825   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71840   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71841   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71842   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71843   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71844   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71845   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71846   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71861   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71862   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71863   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71864   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71865   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71866   { 12866 /* tbuffer_load_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71867   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71882   { 12888 /* tbuffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71883   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71884   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71885   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71886   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71887   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71888   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71896   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71897   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71898   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71899   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71900   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71901   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71902   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71910   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71911   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71912   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71913   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71914   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71915   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71916   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71931   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71932   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71933   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71934   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71935   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71936   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71937   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71952   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71953   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71954   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71955   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71956   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71957   { 12888 /* tbuffer_load_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71958   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71973   { 12911 /* tbuffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71974   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71975   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71976   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71977   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71978   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71979   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
71987   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71988   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
71989   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71990   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71991   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
71992   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71993   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72001   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72002   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72003   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72004   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72005   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72006   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72007   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72022   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72023   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72024   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72025   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72026   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72027   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72028   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72043   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72044   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72045   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72046   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72047   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72048   { 12911 /* tbuffer_load_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72049   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72064   { 12935 /* tbuffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72065   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72066   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72067   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72068   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72069   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72070   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72078   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72079   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72080   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72081   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72082   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72083   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72084   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72092   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72093   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72094   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72095   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72096   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72097   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72098   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72113   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72114   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72115   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72116   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72117   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72118   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72119   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72134   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72135   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72136   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72137   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72138   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72139   { 12935 /* tbuffer_load_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72140   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72491   { 13074 /* tbuffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72492   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72493   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72494   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72495   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72496   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72497   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72505   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72506   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72507   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72508   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72509   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72510   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72511   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72519   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72520   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72521   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72522   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72523   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72524   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72525   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72540   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72541   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72542   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72543   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72544   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72545   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72546   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72561   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72562   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72563   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72564   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72565   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72566   { 13074 /* tbuffer_store_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72567   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72582   { 13097 /* tbuffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72583   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72584   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72585   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72586   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72587   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72588   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72596   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72597   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72598   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72599   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72600   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72601   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72602   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72610   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72611   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72612   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72613   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72614   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72615   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72616   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72631   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72632   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72633   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72634   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72635   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72636   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72637   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72652   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72653   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72654   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72655   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72656   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72657   { 13097 /* tbuffer_store_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72658   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72673   { 13121 /* tbuffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72674   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72675   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72676   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72677   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72678   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72679   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72687   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72688   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72689   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72690   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72691   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72692   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72693   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72701   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72702   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72703   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72704   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72705   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72706   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72707   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72722   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72723   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72724   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72725   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72726   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72727   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72728   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72743   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72744   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72745   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72746   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72747   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72748   { 13121 /* tbuffer_store_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72749   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72764   { 13146 /* tbuffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72765   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72766   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72767   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72768   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72769   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72770   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72778   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72779   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72780   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72781   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72782   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72783   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72784   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72792   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72793   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72794   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72795   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72796   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72797   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72798   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72813   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72814   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72815   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72816   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72817   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72818   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72819   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72834   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72835   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX6GFX7 },
72836   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72837   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72838   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX6GFX7 },
72839   { 13146 /* tbuffer_store_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72840   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX6GFX7 },
72947   { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
72948   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
72949   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
72987   { 13271 /* v_add_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
72988   { 13271 /* v_add_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
72989   { 13271 /* v_add_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
72995   { 13291 /* v_add_i32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
72996   { 13291 /* v_add_i32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73064   { 13402 /* v_addc_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73065   { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73219   { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73220   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
73221   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73283   { 13677 /* v_cmp_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73284   { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73304   { 13713 /* v_cmp_class_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73305   { 13713 /* v_cmp_class_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73329   { 13779 /* v_cmp_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73330   { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73331   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73350   { 13809 /* v_cmp_eq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73351   { 13809 /* v_cmp_eq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73352   { 13809 /* v_cmp_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73371   { 13869 /* v_cmp_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73386   { 13899 /* v_cmp_eq_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73403   { 13959 /* v_cmp_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73418   { 13989 /* v_cmp_eq_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73441   { 14047 /* v_cmp_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73442   { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73443   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73462   { 14075 /* v_cmp_f_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73463   { 14075 /* v_cmp_f_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73464   { 14075 /* v_cmp_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73478   { 14131 /* v_cmp_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73493   { 14159 /* v_cmp_f_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73505   { 14215 /* v_cmp_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73520   { 14243 /* v_cmp_f_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73543   { 14301 /* v_cmp_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73544   { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73545   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73564   { 14331 /* v_cmp_ge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73565   { 14331 /* v_cmp_ge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73566   { 14331 /* v_cmp_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73585   { 14391 /* v_cmp_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73600   { 14421 /* v_cmp_ge_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73617   { 14481 /* v_cmp_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73632   { 14511 /* v_cmp_ge_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73655   { 14571 /* v_cmp_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73656   { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73657   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73676   { 14601 /* v_cmp_gt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73677   { 14601 /* v_cmp_gt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73678   { 14601 /* v_cmp_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73697   { 14661 /* v_cmp_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73712   { 14691 /* v_cmp_gt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73729   { 14751 /* v_cmp_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73744   { 14781 /* v_cmp_gt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73767   { 14841 /* v_cmp_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73768   { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73769   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73788   { 14871 /* v_cmp_le_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73789   { 14871 /* v_cmp_le_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73790   { 14871 /* v_cmp_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73809   { 14931 /* v_cmp_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73824   { 14961 /* v_cmp_le_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73841   { 15021 /* v_cmp_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73856   { 15051 /* v_cmp_le_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73879   { 15111 /* v_cmp_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73880   { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73881   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73900   { 15141 /* v_cmp_lg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73901   { 15141 /* v_cmp_lg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73902   { 15141 /* v_cmp_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73927   { 15201 /* v_cmp_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73928   { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
73929   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73948   { 15231 /* v_cmp_lt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73949   { 15231 /* v_cmp_lt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
73950   { 15231 /* v_cmp_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73969   { 15291 /* v_cmp_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
73984   { 15321 /* v_cmp_lt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74001   { 15381 /* v_cmp_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74016   { 15411 /* v_cmp_lt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74033   { 15471 /* v_cmp_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74048   { 15501 /* v_cmp_ne_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74065   { 15561 /* v_cmp_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74080   { 15591 /* v_cmp_ne_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74103   { 15653 /* v_cmp_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74104   { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74105   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74124   { 15685 /* v_cmp_neq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74125   { 15685 /* v_cmp_neq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74126   { 15685 /* v_cmp_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74151   { 15749 /* v_cmp_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74152   { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74153   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74172   { 15781 /* v_cmp_nge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74173   { 15781 /* v_cmp_nge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74174   { 15781 /* v_cmp_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74199   { 15845 /* v_cmp_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74200   { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74201   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74220   { 15877 /* v_cmp_ngt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74221   { 15877 /* v_cmp_ngt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74222   { 15877 /* v_cmp_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74247   { 15941 /* v_cmp_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74248   { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74249   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74268   { 15973 /* v_cmp_nle_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74269   { 15973 /* v_cmp_nle_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74270   { 15973 /* v_cmp_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74295   { 16037 /* v_cmp_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74296   { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74297   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74316   { 16069 /* v_cmp_nlg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74317   { 16069 /* v_cmp_nlg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74318   { 16069 /* v_cmp_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74343   { 16133 /* v_cmp_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74344   { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74345   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74364   { 16165 /* v_cmp_nlt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74365   { 16165 /* v_cmp_nlt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74366   { 16165 /* v_cmp_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74391   { 16225 /* v_cmp_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74392   { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74393   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74412   { 16253 /* v_cmp_o_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74413   { 16253 /* v_cmp_o_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74414   { 16253 /* v_cmp_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74428   { 16309 /* v_cmp_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74443   { 16337 /* v_cmp_t_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74455   { 16393 /* v_cmp_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74470   { 16421 /* v_cmp_t_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74493   { 16481 /* v_cmp_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74494   { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74495   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74514   { 16513 /* v_cmp_tru_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74515   { 16513 /* v_cmp_tru_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74516   { 16513 /* v_cmp_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74541   { 16573 /* v_cmp_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74542   { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74543   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74562   { 16601 /* v_cmp_u_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74563   { 16601 /* v_cmp_u_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74564   { 16601 /* v_cmp_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74778   { 18811 /* v_cmpx_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74779   { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74797   { 18849 /* v_cmpx_class_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74798   { 18849 /* v_cmpx_class_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74819   { 18919 /* v_cmpx_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74820   { 18919 /* v_cmpx_eq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74821   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74838   { 18951 /* v_cmpx_eq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74839   { 18951 /* v_cmpx_eq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74840   { 18951 /* v_cmpx_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74856   { 19015 /* v_cmpx_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74869   { 19047 /* v_cmpx_eq_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74883   { 19111 /* v_cmpx_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74896   { 19143 /* v_cmpx_eq_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74916   { 19205 /* v_cmpx_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74917   { 19205 /* v_cmpx_f_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
74918   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74935   { 19235 /* v_cmpx_f_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74936   { 19235 /* v_cmpx_f_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
74937   { 19235 /* v_cmpx_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74950   { 19295 /* v_cmpx_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74963   { 19325 /* v_cmpx_f_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74974   { 19385 /* v_cmpx_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
74987   { 19415 /* v_cmpx_f_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75007   { 19477 /* v_cmpx_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75008   { 19477 /* v_cmpx_ge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75009   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75026   { 19509 /* v_cmpx_ge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75027   { 19509 /* v_cmpx_ge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75028   { 19509 /* v_cmpx_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75044   { 19573 /* v_cmpx_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75057   { 19605 /* v_cmpx_ge_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75071   { 19669 /* v_cmpx_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75084   { 19701 /* v_cmpx_ge_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75104   { 19765 /* v_cmpx_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75105   { 19765 /* v_cmpx_gt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75106   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75123   { 19797 /* v_cmpx_gt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75124   { 19797 /* v_cmpx_gt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75125   { 19797 /* v_cmpx_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75141   { 19861 /* v_cmpx_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75154   { 19893 /* v_cmpx_gt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75168   { 19957 /* v_cmpx_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75181   { 19989 /* v_cmpx_gt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75201   { 20053 /* v_cmpx_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75202   { 20053 /* v_cmpx_le_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75203   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75220   { 20085 /* v_cmpx_le_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75221   { 20085 /* v_cmpx_le_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75222   { 20085 /* v_cmpx_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75238   { 20149 /* v_cmpx_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75251   { 20181 /* v_cmpx_le_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75265   { 20245 /* v_cmpx_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75278   { 20277 /* v_cmpx_le_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75298   { 20341 /* v_cmpx_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75299   { 20341 /* v_cmpx_lg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75300   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75317   { 20373 /* v_cmpx_lg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75318   { 20373 /* v_cmpx_lg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75319   { 20373 /* v_cmpx_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75341   { 20437 /* v_cmpx_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75342   { 20437 /* v_cmpx_lt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75343   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75360   { 20469 /* v_cmpx_lt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75361   { 20469 /* v_cmpx_lt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75362   { 20469 /* v_cmpx_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75378   { 20533 /* v_cmpx_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75391   { 20565 /* v_cmpx_lt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75405   { 20629 /* v_cmpx_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75418   { 20661 /* v_cmpx_lt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75432   { 20725 /* v_cmpx_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75445   { 20757 /* v_cmpx_ne_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75459   { 20821 /* v_cmpx_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75472   { 20853 /* v_cmpx_ne_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75492   { 20919 /* v_cmpx_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75493   { 20919 /* v_cmpx_neq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75494   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75511   { 20953 /* v_cmpx_neq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75512   { 20953 /* v_cmpx_neq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75513   { 20953 /* v_cmpx_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75535   { 21021 /* v_cmpx_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75536   { 21021 /* v_cmpx_nge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75537   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75554   { 21055 /* v_cmpx_nge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75555   { 21055 /* v_cmpx_nge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75556   { 21055 /* v_cmpx_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75578   { 21123 /* v_cmpx_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75579   { 21123 /* v_cmpx_ngt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75580   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75597   { 21157 /* v_cmpx_ngt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75598   { 21157 /* v_cmpx_ngt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75599   { 21157 /* v_cmpx_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75621   { 21225 /* v_cmpx_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75622   { 21225 /* v_cmpx_nle_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75623   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75640   { 21259 /* v_cmpx_nle_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75641   { 21259 /* v_cmpx_nle_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75642   { 21259 /* v_cmpx_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75664   { 21327 /* v_cmpx_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75665   { 21327 /* v_cmpx_nlg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75666   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75683   { 21361 /* v_cmpx_nlg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75684   { 21361 /* v_cmpx_nlg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75685   { 21361 /* v_cmpx_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75707   { 21429 /* v_cmpx_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75708   { 21429 /* v_cmpx_nlt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75709   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75726   { 21463 /* v_cmpx_nlt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75727   { 21463 /* v_cmpx_nlt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75728   { 21463 /* v_cmpx_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75750   { 21527 /* v_cmpx_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75751   { 21527 /* v_cmpx_o_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75752   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75769   { 21557 /* v_cmpx_o_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75770   { 21557 /* v_cmpx_o_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75771   { 21557 /* v_cmpx_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75784   { 21617 /* v_cmpx_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75797   { 21647 /* v_cmpx_t_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75808   { 21707 /* v_cmpx_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75821   { 21737 /* v_cmpx_t_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75841   { 21801 /* v_cmpx_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75842   { 21801 /* v_cmpx_tru_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75843   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75860   { 21835 /* v_cmpx_tru_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75861   { 21835 /* v_cmpx_tru_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75862   { 21835 /* v_cmpx_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75884   { 21899 /* v_cmpx_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75885   { 21899 /* v_cmpx_u_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
75886   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75903   { 21929 /* v_cmpx_u_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75904   { 21929 /* v_cmpx_u_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
75905   { 21929 /* v_cmpx_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75911   { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
75912   { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76011   { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76012   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76013   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76048   { 21993 /* v_cubeid_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76049   { 21993 /* v_cubeid_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76050   { 21993 /* v_cubeid_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76057   { 22006 /* v_cubema_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76058   { 22006 /* v_cubema_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76059   { 22006 /* v_cubema_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76066   { 22019 /* v_cubesc_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76067   { 22019 /* v_cubesc_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76068   { 22019 /* v_cubesc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76075   { 22032 /* v_cubetc_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76076   { 22032 /* v_cubetc_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76077   { 22032 /* v_cubetc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76086   { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76087   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76088   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76189   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX6GFX7 },
76190   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76191   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76226   { 22101 /* v_cvt_f32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
76227   { 22101 /* v_cvt_f32_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76228   { 22101 /* v_cvt_f32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76236   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76237   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76270   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76271   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76304   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76305   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76338   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76339   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76372   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76373   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76406   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76407   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76439   { 22211 /* v_cvt_f64_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76440   { 22211 /* v_cvt_f64_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76441   { 22211 /* v_cvt_f64_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76447   { 22225 /* v_cvt_f64_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76448   { 22225 /* v_cvt_f64_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76453   { 22239 /* v_cvt_f64_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76454   { 22239 /* v_cvt_f64_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76459   { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76460   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76525   { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76526   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76559   { 22299 /* v_cvt_i32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
76560   { 22299 /* v_cvt_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76631   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76632   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76664   { 22402 /* v_cvt_pk_u8_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76665   { 22402 /* v_cvt_pk_u8_f32 */, 12 /* 2, 3 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 },
76666   { 22402 /* v_cvt_pk_u8_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76670   { 22418 /* v_cvt_pkaccum_u8_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76671   { 22418 /* v_cvt_pkaccum_u8_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 },
76672   { 22418 /* v_cvt_pkaccum_u8_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76684   { 22460 /* v_cvt_pknorm_i16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76685   { 22460 /* v_cvt_pknorm_i16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76696   { 22502 /* v_cvt_pknorm_u16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76697   { 22502 /* v_cvt_pknorm_u16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76703   { 22523 /* v_cvt_pkrtz_f16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76704   { 22523 /* v_cvt_pkrtz_f16_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76705   { 22523 /* v_cvt_pkrtz_f16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76711   { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76712   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76777   { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76778   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76811   { 22589 /* v_cvt_u32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
76812   { 22589 /* v_cvt_u32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76827   { 22619 /* v_div_fixup_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76828   { 22619 /* v_div_fixup_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76829   { 22619 /* v_div_fixup_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76836   { 22635 /* v_div_fixup_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
76837   { 22635 /* v_div_fixup_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76838   { 22635 /* v_div_fixup_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76848   { 22674 /* v_div_fmas_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
76849   { 22674 /* v_div_fmas_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76850   { 22674 /* v_div_fmas_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76857   { 22689 /* v_div_fmas_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
76858   { 22689 /* v_div_fmas_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
76859   { 22689 /* v_div_fmas_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76864   { 22704 /* v_div_scale_f32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
76867   { 22720 /* v_div_scale_f64 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
77016   { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77017   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77018   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77191   { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77192   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77193   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77246   { 23015 /* v_fma_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77247   { 23015 /* v_fma_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77248   { 23015 /* v_fma_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77255   { 23025 /* v_fma_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
77256   { 23025 /* v_fma_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77257   { 23025 /* v_fma_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77369   { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77370   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77371   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77406   { 23192 /* v_fract_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
77407   { 23192 /* v_fract_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77408   { 23192 /* v_fract_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77446   { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77447   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77480   { 23244 /* v_frexp_exp_i32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
77481   { 23244 /* v_frexp_exp_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77525   { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77526   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77527   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77562   { 23298 /* v_frexp_mant_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
77563   { 23298 /* v_frexp_mant_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77564   { 23298 /* v_frexp_mant_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77570   { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77571   { 23315 /* v_interp_mov_f32 */, 2 /* 1 */, MCK_InterpSlot, AMFBS_isGFX6GFX7 },
77583   { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77586   { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77631   { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77695   { 23451 /* v_ldexp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77696   { 23451 /* v_ldexp_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 },
77697   { 23451 /* v_ldexp_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77698   { 23451 /* v_ldexp_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77707   { 23463 /* v_ldexp_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
77708   { 23463 /* v_ldexp_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 },
77709   { 23463 /* v_ldexp_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77710   { 23463 /* v_ldexp_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77759   { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77760   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77761   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77924   { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77925   { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77926   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77977   { 23742 /* v_mad_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
77978   { 23742 /* v_mad_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
77979   { 23742 /* v_mad_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77993   { 23776 /* v_mad_i32_i24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78007   { 23821 /* v_mad_legacy_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78008   { 23821 /* v_mad_legacy_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78009   { 23821 /* v_mad_legacy_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78037   { 23942 /* v_mad_u32_u24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78047   { 23982 /* v_madak_f32 */, 8 /* 3 */, MCK_KImmFP32, AMFBS_isGFX6GFX7 },
78051   { 24006 /* v_madmk_f32 */, 4 /* 2 */, MCK_KImmFP32, AMFBS_isGFX6GFX7 },
78062   { 24029 /* v_max3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78063   { 24029 /* v_max3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78064   { 24029 /* v_max3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78120   { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78121   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78122   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78160   { 24104 /* v_max_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
78161   { 24104 /* v_max_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78162   { 24104 /* v_max_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78268   { 24220 /* v_med3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78269   { 24220 /* v_med3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78270   { 24220 /* v_med3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78351   { 24720 /* v_min3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78352   { 24720 /* v_min3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78353   { 24720 /* v_min3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78409   { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78410   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78411   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78449   { 24795 /* v_min_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
78450   { 24795 /* v_min_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78451   { 24795 /* v_min_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78601   { 24946 /* v_mqsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78607   { 24979 /* v_msad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78653   { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78654   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78655   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78693   { 25009 /* v_mul_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
78694   { 25009 /* v_mul_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78695   { 25009 /* v_mul_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78791   { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
78792   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
78793   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79182   { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79183   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79184   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79219   { 25629 /* v_rcp_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
79220   { 25629 /* v_rcp_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79221   { 25629 /* v_rcp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79230   { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79231   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79232   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79308   { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79309   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79310   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79398   { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79399   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79400   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79435   { 25795 /* v_rsq_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
79436   { 25795 /* v_rsq_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79437   { 25795 /* v_rsq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79445   { 25822 /* v_sad_hi_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79448   { 25834 /* v_sad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79451   { 25844 /* v_sad_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79454   { 25854 /* v_sad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79532   { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79533   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79534   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79607   { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79608   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79609   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79644   { 25948 /* v_sqrt_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
79645   { 25948 /* v_sqrt_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79646   { 25948 /* v_sqrt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79749   { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79750   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79751   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79788   { 26018 /* v_sub_i32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
79789   { 26018 /* v_sub_i32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79857   { 26114 /* v_subb_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
79858   { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79883   { 26142 /* v_subbrev_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
79884   { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79996   { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
79997   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
79998   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80033   { 26217 /* v_subrev_i32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX6GFX7 },
80034   { 26217 /* v_subrev_i32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80092   { 26297 /* v_trig_preop_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX6GFX7 },
80093   { 26297 /* v_trig_preop_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 },
80094   { 26297 /* v_trig_preop_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
80095   { 26297 /* v_trig_preop_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80141   { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX6GFX7 },
80142   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX6GFX7 },
80143   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },