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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18852 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21047 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21373 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21399 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21440 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22110 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22722 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22754 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22793 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22944 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23032 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23046 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23061 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23348 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23510 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23531 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23557 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23601 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23851 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23881 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },