reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
18853 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 21050 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 21374 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 21400 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 21441 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 22113 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 22723 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 22755 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 22794 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 22947 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23033 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23047 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23062 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23351 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23511 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23532 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23558 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23604 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23852 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, }, 23882 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },