reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

11077   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11080   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11084   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11087   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11091   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11094   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11097   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11100   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11107   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11110   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11114   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11117   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11121   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11124   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11127   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11130   { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11133   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11136   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11140   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11143   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11147   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11150   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11153   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11156   { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11159   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11162   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11166   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11169   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11173   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11176   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11179   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11182   { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11185   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11188   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11192   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11195   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11199   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11202   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11205   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11208   { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11211   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11214   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11218   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11221   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11225   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11228   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11231   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11234   { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11237   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11240   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11244   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11247   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11251   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11254   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11257   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11260   { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11263   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11266   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11270   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11273   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11277   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11280   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11283   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11286   { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11397   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11400   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11404   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11407   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11411   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11414   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11417   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11420   { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11423   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11426   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11430   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11433   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11437   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11440   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11443   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11446   { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11449   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11452   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11456   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11459   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11463   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11466   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11469   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11472   { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11475   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11478   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11482   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11485   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11489   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11492   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11495   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11498   { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11505   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11508   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11512   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11515   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11519   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11522   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11525   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11528   { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11531   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11534   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11538   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11541   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11545   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11548   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11551   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11554   { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11557   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11560   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11564   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11567   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11571   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11574   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11577   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11580   { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11583   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11586   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11590   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11593   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11597   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11600   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11603   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11606   { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11609   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11612   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11616   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11619   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11623   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11626   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11629   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11632   { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11635   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11638   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11642   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11645   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11649   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11652   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11655   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11658   { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11661   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11664   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11668   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11671   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11675   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11678   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11681   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11684   { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11687   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11690   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11694   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11697   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11701   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11704   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11707   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11710   { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11713   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11716   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11720   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11723   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11727   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11730   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11733   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11736   { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11739   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11742   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11746   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11749   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11753   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11756   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11759   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11762   { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11765   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11768   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11772   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11775   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11779   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11782   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11785   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11788   { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11791   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11794   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11798   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11801   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11805   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11808   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11811   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11814   { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11817   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11820   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11824   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11827   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11831   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11834   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11837   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11840   { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11843   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11846   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11850   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11853   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11857   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11860   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11863   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11866   { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11869   { 701 /* buffer_gl0_inv */, AMDGPU::BUFFER_GL0_INV_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
11870   { 716 /* buffer_gl1_inv */, AMDGPU::BUFFER_GL1_INV_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
11871   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11874   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11879   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11882   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11885   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11888   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11891   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11894   { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11898   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11903   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11907   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11911   { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11915   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11920   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11924   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11928   { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11932   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11937   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11941   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11945   { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12000   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12003   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12008   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12011   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12014   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12017   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12020   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12023   { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12026   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12030   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12033   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12036   { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12039   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12043   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12046   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12049   { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12052   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12056   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12059   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12062   { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12065   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12068   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12073   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12076   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12079   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12082   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12085   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12088   { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12123   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12126   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12131   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12134   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12137   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12140   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12143   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12146   { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12149   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12152   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12157   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12160   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12163   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12166   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12169   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12172   { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12191   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12194   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12199   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12202   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12205   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12208   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12211   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12214   { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12217   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12221   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12224   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12227   { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12238   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12242   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12245   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12248   { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12251   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12255   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12258   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12261   { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12264   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12268   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12271   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12274   { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12277   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12281   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12284   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12287   { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12342   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12346   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12349   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12352   { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12355   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12359   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12362   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12365   { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12368   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12372   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12375   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12378   { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12381   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12385   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12388   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12391   { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12395   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12399   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12402   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12405   { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12421   { 1726 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12423   { 1737 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12425   { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12428   { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12433   { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12436   { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12439   { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12442   { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12445   { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12448   { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12451   { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12454   { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12457   { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12460   { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12463   { 1936 /* ds_append */, AMDGPU::DS_APPEND_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12468   { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12471   { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12474   { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12477   { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12480   { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12483   { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12486   { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12489   { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12495   { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12498   { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12501   { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12504   { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12507   { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12510   { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12513   { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12516   { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12519   { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12522   { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12525   { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12531   { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12534   { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12537   { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12540   { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12543   { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12546   { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12549   { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12552   { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12555   { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12558   { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12561   { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12564   { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12567   { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12570   { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12573   { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12576   { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12579   { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12582   { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12585   { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12588   { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12591   { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12594   { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12597   { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12600   { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12603   { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12606   { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12609   { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12612   { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12615   { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12618   { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12621   { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12624   { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12627   { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12630   { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12633   { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12636   { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12639   { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12642   { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12645   { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12648   { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12651   { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12654   { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12657   { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12660   { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12663   { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12666   { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12669   { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12675   { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12678   { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12681   { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12684   { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12687   { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12690   { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12693   { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12698   { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12701   { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12704   { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12707   { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12715   { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12718   { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12724   { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12727   { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12734   { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12741   { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12748   { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12751   { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12754   { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12757   { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12760   { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12763   { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12766   { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12769   { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12772   { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12775   { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12778   { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12781   { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12784   { 3507 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
12790   { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12793   { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12796   { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12799   { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12807   { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12812   { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12815   { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12818   { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12826   { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12829   { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12832   { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12835   { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12838   { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12841   { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12844   { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12847   { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12850   { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12853   { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12856   { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12859   { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12862   { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12865   { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12868   { 3979 /* exp */, AMDGPU::EXP_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12871   { 3979 /* exp */, AMDGPU::EXP_DONE_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
17541   { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17544   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17547   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17550   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17553   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17556   { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_gfx10, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
17559   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17562   { 7827 /* s_and_b64 */, AMDGPU::S_AND_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17566   { 7856 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17575   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17578   { 7967 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17582   { 8000 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17588   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17591   { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17811   { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17814   { 8531 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
17817   { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17820   { 8563 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
17823   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17826   { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17829   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17832   { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17835   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17838   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17847   { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17850   { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17853   { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17856   { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17861   { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17864   { 8794 /* s_brev_b64 */, AMDGPU::S_BREV_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18075   { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18079   { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18082   { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18086   { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18089   { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18093   { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18096   { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18100   { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18103   { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18107   { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18150   { 9800 /* s_clause */, AMDGPU::S_CLAUSE, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18151   { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18154   { 9820 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18157   { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18174   { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18177   { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18180   { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18183   { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18186   { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18189   { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18192   { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18195   { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18198   { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18201   { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18204   { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18207   { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18210   { 10193 /* s_code_end */, AMDGPU::S_CODE_END, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
18211   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18214   { 10218 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18225   { 10269 /* s_dcache_inv */, AMDGPU::S_DCACHE_INV_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
18234   { 10342 /* s_denorm_mode */, AMDGPU::S_DENORM_MODE, Convert__Imm1_0, AMFBS_isGFX10Plus, { MCK_Imm }, },
18238   { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18241   { 10419 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18244   { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18247   { 10447 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18250   { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18253   { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18256   { 10489 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18259   { 10505 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18263   { 10547 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64 }, },
18266   { 10559 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_gfx10, Convert__Reg1_0__ImmHwreg1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_ImmHwreg }, },
18272   { 10610 /* s_inst_prefetch */, AMDGPU::S_INST_PREFETCH, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18273   { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18277   { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18280   { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18284   { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18287   { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18291   { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18294   { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18298   { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18301   { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18305   { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18316   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18319   { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18322   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18325   { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18328   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18331   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18336   { 10842 /* s_memtime */, AMDGPU::S_MEMTIME_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC }, },
18339   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18342   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18345   { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18348   { 10882 /* s_mov_b64 */, AMDGPU::S_MOV_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18351   { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18356   { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18359   { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18362   { 10947 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18365   { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18368   { 10975 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18376   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18379   { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_gfx10, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18382   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18385   { 11064 /* s_nand_b64 */, AMDGPU::S_NAND_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18389   { 11095 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18393   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18396   { 11131 /* s_nor_b64 */, AMDGPU::S_NOR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18400   { 11160 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18403   { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18406   { 11189 /* s_not_b64 */, AMDGPU::S_NOT_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18409   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18412   { 11208 /* s_or_b64 */, AMDGPU::S_OR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18416   { 11235 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18422   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18425   { 11304 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18429   { 11335 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18438   { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18441   { 11424 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18444   { 11439 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64 }, },
18448   { 11467 /* s_round_mode */, AMDGPU::S_ROUND_MODE, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18481   { 11733 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64 }, },
18485   { 11755 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_gfx10, Convert__Reg1_1__ImmHwreg1_0, AMFBS_isGFX10Plus, { MCK_ImmHwreg, MCK_SReg_32 }, },
18488   { 11768 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_gfx10, Convert__Imm1_1__ImmHwreg1_0, AMFBS_isGFX10Plus, { MCK_ImmHwreg, MCK_Imm }, },
18492   { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18495   { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18511   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18514   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18517   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18522   { 11956 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18527   { 11989 /* s_ttracedata_imm */, AMDGPU::S_TTRACEDATA_IMM, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18529   { 12016 /* s_wait_idle */, AMDGPU::S_WAITCNT_IDLE, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
18531   { 12038 /* s_waitcnt_depctr */, AMDGPU::S_WAITCNT_DEPCTR, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18537   { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18540   { 12141 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18543   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18546   { 12162 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18550   { 12193 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18553   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18556   { 12223 /* s_xor_b64 */, AMDGPU::S_XOR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18560   { 12252 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18699   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18703   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18706   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18709   { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18712   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18716   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18719   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18722   { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18725   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18729   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18732   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18735   { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18738   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18742   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18745   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18748   { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18799   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18803   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18806   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18809   { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18812   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18816   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18819   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18822   { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18825   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18829   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18832   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18835   { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18838   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18842   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18845   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18848   { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18851   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18859   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
18872   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18877   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18882   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
18887   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
18893   { 13631 /* v_clrexcp */, AMDGPU::V_CLREXCP_e32_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
18913   { 13693 /* v_cmp_class_f32_e32 */, AMDGPU::V_CMP_CLASS_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
18925   { 13729 /* v_cmp_class_f64_e32 */, AMDGPU::V_CMP_CLASS_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VGPR_32 }, },
18945   { 13792 /* v_cmp_eq_f32_e32 */, AMDGPU::V_CMP_EQ_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
18957   { 13822 /* v_cmp_eq_f64_e32 */, AMDGPU::V_CMP_EQ_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
18977   { 13882 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
18989   { 13912 /* v_cmp_eq_i64_e32 */, AMDGPU::V_CMP_EQ_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19009   { 13972 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19021   { 14002 /* v_cmp_eq_u64_e32 */, AMDGPU::V_CMP_EQ_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19041   { 14059 /* v_cmp_f_f32_e32 */, AMDGPU::V_CMP_F_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19053   { 14087 /* v_cmp_f_f64_e32 */, AMDGPU::V_CMP_F_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19069   { 14143 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19081   { 14171 /* v_cmp_f_i64_e32 */, AMDGPU::V_CMP_F_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19097   { 14227 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19109   { 14255 /* v_cmp_f_u64_e32 */, AMDGPU::V_CMP_F_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19129   { 14314 /* v_cmp_ge_f32_e32 */, AMDGPU::V_CMP_GE_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19141   { 14344 /* v_cmp_ge_f64_e32 */, AMDGPU::V_CMP_GE_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19161   { 14404 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19173   { 14434 /* v_cmp_ge_i64_e32 */, AMDGPU::V_CMP_GE_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19193   { 14494 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19205   { 14524 /* v_cmp_ge_u64_e32 */, AMDGPU::V_CMP_GE_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19225   { 14584 /* v_cmp_gt_f32_e32 */, AMDGPU::V_CMP_GT_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19237   { 14614 /* v_cmp_gt_f64_e32 */, AMDGPU::V_CMP_GT_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19257   { 14674 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19269   { 14704 /* v_cmp_gt_i64_e32 */, AMDGPU::V_CMP_GT_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19289   { 14764 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19301   { 14794 /* v_cmp_gt_u64_e32 */, AMDGPU::V_CMP_GT_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19321   { 14854 /* v_cmp_le_f32_e32 */, AMDGPU::V_CMP_LE_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19333   { 14884 /* v_cmp_le_f64_e32 */, AMDGPU::V_CMP_LE_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19353   { 14944 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19365   { 14974 /* v_cmp_le_i64_e32 */, AMDGPU::V_CMP_LE_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19385   { 15034 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19397   { 15064 /* v_cmp_le_u64_e32 */, AMDGPU::V_CMP_LE_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19417   { 15124 /* v_cmp_lg_f32_e32 */, AMDGPU::V_CMP_LG_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19429   { 15154 /* v_cmp_lg_f64_e32 */, AMDGPU::V_CMP_LG_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19449   { 15214 /* v_cmp_lt_f32_e32 */, AMDGPU::V_CMP_LT_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19461   { 15244 /* v_cmp_lt_f64_e32 */, AMDGPU::V_CMP_LT_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19481   { 15304 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19493   { 15334 /* v_cmp_lt_i64_e32 */, AMDGPU::V_CMP_LT_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19513   { 15394 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19525   { 15424 /* v_cmp_lt_u64_e32 */, AMDGPU::V_CMP_LT_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19545   { 15484 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19557   { 15514 /* v_cmp_ne_i64_e32 */, AMDGPU::V_CMP_NE_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19577   { 15574 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19589   { 15604 /* v_cmp_ne_u64_e32 */, AMDGPU::V_CMP_NE_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19609   { 15667 /* v_cmp_neq_f32_e32 */, AMDGPU::V_CMP_NEQ_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19621   { 15699 /* v_cmp_neq_f64_e32 */, AMDGPU::V_CMP_NEQ_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19641   { 15763 /* v_cmp_nge_f32_e32 */, AMDGPU::V_CMP_NGE_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19653   { 15795 /* v_cmp_nge_f64_e32 */, AMDGPU::V_CMP_NGE_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19673   { 15859 /* v_cmp_ngt_f32_e32 */, AMDGPU::V_CMP_NGT_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19685   { 15891 /* v_cmp_ngt_f64_e32 */, AMDGPU::V_CMP_NGT_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19705   { 15955 /* v_cmp_nle_f32_e32 */, AMDGPU::V_CMP_NLE_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19717   { 15987 /* v_cmp_nle_f64_e32 */, AMDGPU::V_CMP_NLE_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19737   { 16051 /* v_cmp_nlg_f32_e32 */, AMDGPU::V_CMP_NLG_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19749   { 16083 /* v_cmp_nlg_f64_e32 */, AMDGPU::V_CMP_NLG_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19769   { 16147 /* v_cmp_nlt_f32_e32 */, AMDGPU::V_CMP_NLT_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19781   { 16179 /* v_cmp_nlt_f64_e32 */, AMDGPU::V_CMP_NLT_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19801   { 16237 /* v_cmp_o_f32_e32 */, AMDGPU::V_CMP_O_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19813   { 16265 /* v_cmp_o_f64_e32 */, AMDGPU::V_CMP_O_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19829   { 16321 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19841   { 16349 /* v_cmp_t_i64_e32 */, AMDGPU::V_CMP_T_I64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19857   { 16405 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19869   { 16433 /* v_cmp_t_u64_e32 */, AMDGPU::V_CMP_T_U64_e32_gfx10, Convert__VSrcB641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB64, MCK_VReg_64 }, },
19889   { 16495 /* v_cmp_tru_f32_e32 */, AMDGPU::V_CMP_TRU_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19901   { 16527 /* v_cmp_tru_f64_e32 */, AMDGPU::V_CMP_TRU_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
19921   { 16585 /* v_cmp_u_f32_e32 */, AMDGPU::V_CMP_U_F32_e32_gfx10, Convert__VSrcF321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF32, MCK_VGPR_32 }, },
19933   { 16613 /* v_cmp_u_f64_e32 */, AMDGPU::V_CMP_U_F64_e32_gfx10, Convert__VSrcF641_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcF64, MCK_VReg_64 }, },
21042   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21053   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21056   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21063   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21066   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21069   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21072   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21075   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21078   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21081   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21084   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21087   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF32 }, },
21090   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32 }, },
21093   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32 }, },
21096   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21101   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21104   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21111   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21119   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21121   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21126   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21129   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21140   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21145   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21148   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21151   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21156   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21171   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21174   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21179   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21182   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21187   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21190   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21193   { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_gfx10, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
21196   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_gfx10, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21199   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_gfx10, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21202   { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21211   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21218   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21223   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21227   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21233   { 23982 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_gfx10, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, },
21237   { 24006 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_gfx10, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, },
21242   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21246   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21251   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21258   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21262   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21267   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21270   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21273   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21288   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21291   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21294   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21297   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21300   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21304   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21307   { 25176 /* v_nop */, AMDGPU::V_NOP_e32_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
21310   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21313   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21323   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21326   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21329   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21334   { 25692 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_gfx10, Convert__Reg1_0__Reg1_1__SCSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_VRegOrLds_32, MCK_SCSrcB32 }, },
21339   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21349   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21352   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21361   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21366   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21369   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21372   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21380   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21398   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21406   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21419   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21425   { 26350 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_gfx10, Convert__Reg1_0__SSrcOrLdsB321_1__SCSrcB321_2__Tie0_1_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_SSrcOrLdsB32, MCK_SCSrcB32 }, },
21430   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21442   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21445   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21449   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21452   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21472   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21475   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21478   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21487   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21492   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21495   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21498   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21501   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21504   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21507   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21512   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21518   { 13631 /* v_clrexcp */, AMDGPU::V_CLREXCP_e64_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
21523   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21526   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21531   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21534   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21539   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21542   { 13899 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21547   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21550   { 13989 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21555   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21558   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21562   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21565   { 14159 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21569   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21572   { 14243 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21577   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21580   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21585   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21588   { 14421 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21593   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21596   { 14511 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21601   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21604   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21609   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21612   { 14691 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21617   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21620   { 14781 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21625   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21628   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21633   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21636   { 14961 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21641   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21644   { 15051 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21649   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21652   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21657   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21660   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21665   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21668   { 15321 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21673   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21676   { 15411 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21681   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21684   { 15501 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21689   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21692   { 15591 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21697   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21700   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21705   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21708   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21713   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21716   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21721   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21724   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21729   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21732   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21737   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21740   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21745   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21748   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21752   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21755   { 16337 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21759   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21762   { 16421 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_gfx10, Convert__BoolReg1_0__VSrcB641_1__VSrcB641_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB64, MCK_VSrcB64 }, },
21767   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21770   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21775   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21778   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22105   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_BoolReg }, },
22116   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22119   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22122   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22125   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22128   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22131   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22138   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22141   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22144   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22147   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22150   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22153   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22156   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22159   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22162   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22165   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22168   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22171   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22176   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22179   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22186   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22189   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22192   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22195   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22204   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22210   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22214   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22217   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22222   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22225   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22229   { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22231   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22234   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22238   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22241   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22244   { 22704 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_gfx10, Convert__Reg1_0__BoolReg1_1__VSrcF321_2__VSrcF321_3__VSrcF321_4, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcF32, MCK_VSrcF32, MCK_VSrcF32 }, },
22247   { 22720 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_gfx10, Convert__Reg1_0__BoolReg1_1__VSrcF641_2__VSrcF641_3__VSrcF641_4, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcF64, MCK_VSrcF64, MCK_VSrcF64 }, },
22266   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22271   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22274   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22277   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22282   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22289   { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22291   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22294   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22309   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22312   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22317   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22320   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22325   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22328   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22348   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22351   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22354   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22360   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22373   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22382   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22388   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22395   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22403   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22410   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22423   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22431   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22436   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22441   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22446   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22449   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22454   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22460   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22463   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22466   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22471   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22476   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22481   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22506   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22511   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22516   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22521   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22524   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22529   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22535   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22538   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22541   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22554   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22560   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22565   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22568   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22571   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22574   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22577   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22580   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22583   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22586   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22589   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22594   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22597   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22602   { 25176 /* v_nop */, AMDGPU::V_NOP_e64_gfx10, Convert_NoOperands, AMFBS_isGFX10Plus, {  }, },
22605   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22610   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22620   { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22622   { 25297 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22624   { 25310 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22626   { 25323 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22628   { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22630   { 25367 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22632   { 25384 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22634   { 25401 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22636   { 25414 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22638   { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22640   { 25440 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22642   { 25453 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22644   { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22646   { 25479 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22648   { 25492 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22650   { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22652   { 25518 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22654   { 25534 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22656   { 25547 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22665   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22668   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22671   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22677   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22687   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22690   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22694   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22697   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22700   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22703   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22711   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22716   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22719   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22724   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22727   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22731   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22756   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22759   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22763   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22771   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22776   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22787   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
24157   { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24158   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24163   { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24164   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24171   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24172   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24177   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24178   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24185   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24186   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24191   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24192   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24197   { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24198   { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24203   { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24204   { 0 /* buffer_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24217   { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24218   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24223   { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24224   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24231   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24232   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24237   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24238   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24245   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24246   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24251   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24252   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24257   { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24258   { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24263   { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24264   { 40 /* buffer_atomic_add_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24269   { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24270   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24275   { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24276   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24283   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24284   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24289   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24290   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24297   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24298   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24303   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24304   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24309   { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24310   { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24315   { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24316   { 61 /* buffer_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24321   { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24322   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24327   { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24328   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24335   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24336   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24341   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24342   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24349   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24350   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24355   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24356   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24361   { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24362   { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24367   { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24368   { 79 /* buffer_atomic_and_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24373   { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24374   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24379   { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24380   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24387   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24388   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24393   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24394   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24401   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24402   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24407   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24408   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24413   { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24414   { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24419   { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24420   { 100 /* buffer_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24425   { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24426   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24431   { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24432   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24439   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24440   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24445   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24446   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24453   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24454   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24459   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24460   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24465   { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24466   { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24471   { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24472   { 122 /* buffer_atomic_cmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24477   { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24478   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24483   { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24484   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24491   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24492   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24497   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24498   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24505   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24506   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24511   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24512   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24517   { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24518   { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24523   { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24524   { 147 /* buffer_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24529   { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24530   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24535   { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24536   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24543   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24544   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24549   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24550   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24557   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24558   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24563   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24564   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24569   { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24570   { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24575   { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24576   { 165 /* buffer_atomic_dec_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24797   { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24798   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24803   { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24804   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24811   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24812   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24817   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24818   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24825   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24826   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24831   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24832   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24837   { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24838   { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24843   { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24844   { 317 /* buffer_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24849   { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24850   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24855   { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24856   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24863   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24864   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24869   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24870   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24877   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24878   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24883   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24884   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24889   { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24890   { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24895   { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24896   { 335 /* buffer_atomic_inc_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24901   { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24902   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24907   { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24908   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24915   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24916   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24921   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24922   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24929   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24930   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24935   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24936   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24941   { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24942   { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24947   { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24948   { 356 /* buffer_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24953   { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24954   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24959   { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24960   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24967   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24968   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24973   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24974   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24981   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24982   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24987   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24988   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24993   { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24994   { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24999   { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25000   { 373 /* buffer_atomic_or_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25013   { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25014   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25019   { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25020   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25027   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25028   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25033   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25034   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25041   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25042   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25047   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25048   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25053   { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25054   { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25059   { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25060   { 418 /* buffer_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25065   { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25066   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25071   { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25072   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25079   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25080   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25085   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25086   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25093   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25094   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25099   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25100   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25105   { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25106   { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25111   { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25112   { 437 /* buffer_atomic_smax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25117   { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25118   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25123   { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25124   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25131   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25132   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25137   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25138   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25145   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25146   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25151   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25152   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25157   { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25158   { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25163   { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25164   { 459 /* buffer_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25169   { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25170   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25175   { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25176   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25183   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25184   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25189   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25190   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25197   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25198   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25203   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25204   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25209   { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25210   { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25215   { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25216   { 478 /* buffer_atomic_smin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25221   { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25222   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25227   { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25228   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25235   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25236   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25241   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25242   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25249   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25250   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25255   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25256   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25261   { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25262   { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25267   { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25268   { 500 /* buffer_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25273   { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25274   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25279   { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25280   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25287   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25288   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25293   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25294   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25301   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25302   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25307   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25308   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25313   { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25314   { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25319   { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25320   { 518 /* buffer_atomic_sub_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25325   { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25326   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25331   { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25332   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25339   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25340   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25345   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25346   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25353   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25354   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25359   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25360   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25365   { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25366   { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25371   { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25372   { 539 /* buffer_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25377   { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25378   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25383   { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25384   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25391   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25392   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25397   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25398   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25405   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25406   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25411   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25412   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25417   { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25418   { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25423   { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25424   { 558 /* buffer_atomic_swap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25429   { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25430   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25435   { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25436   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25443   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25444   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25449   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25450   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25457   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25458   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25463   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25464   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25469   { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25470   { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25475   { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25476   { 580 /* buffer_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25481   { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25482   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25487   { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25488   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25495   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25496   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25501   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25502   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25509   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25510   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25515   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25516   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25521   { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25522   { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25527   { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25528   { 599 /* buffer_atomic_umax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25533   { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25534   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25539   { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25540   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25547   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25548   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25553   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25554   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25561   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25562   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25567   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25568   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25573   { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25574   { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25579   { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25580   { 621 /* buffer_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25585   { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25586   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25591   { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25592   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25599   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25600   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25605   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25606   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25613   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25614   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25619   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25620   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25625   { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25626   { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25631   { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25632   { 640 /* buffer_atomic_umin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25637   { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25638   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25643   { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25644   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25651   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25652   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25657   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25658   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25665   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25666   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25671   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25672   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25677   { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25678   { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25683   { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25684   { 662 /* buffer_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25689   { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25690   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25695   { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25696   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25703   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25704   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25709   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25710   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25717   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25718   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25723   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25724   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25729   { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25730   { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25735   { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25736   { 680 /* buffer_atomic_xor_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25741   { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25742   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25743   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25744   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25745   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25756   { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25757   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25758   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25759   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25760   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25761   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25785   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25786   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25787   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25788   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25789   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25800   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25801   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25802   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25803   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25804   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25805   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25818   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25819   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25820   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25821   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25822   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25833   { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25834   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25835   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25836   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25837   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25838   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25851   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25852   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25853   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25854   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25855   { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25866   { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25867   { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25868   { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25869   { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25870   { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25871   { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25889   { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25890   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25891   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25892   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25893   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25894   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25918   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25919   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25920   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25921   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25922   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25923   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25941   { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25942   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25943   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25944   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25945   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25946   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25964   { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25965   { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25966   { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25967   { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25968   { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25969   { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25987   { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25988   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
25989   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25990   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25991   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
25992   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26016   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26017   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26018   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26019   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26020   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26021   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26039   { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26040   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26041   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26042   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26043   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26044   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26062   { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26063   { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26064   { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26065   { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26066   { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26067   { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26085   { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26086   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26087   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26088   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26089   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26090   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26114   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26115   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26116   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26117   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26118   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26119   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26137   { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26138   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26139   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26140   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26141   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26142   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26160   { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26161   { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26162   { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26163   { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26164   { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26165   { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26490   { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26491   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26492   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26493   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26494   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26505   { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26506   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26507   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26508   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26509   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26510   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26534   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26535   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26536   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26537   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26538   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26549   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26550   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26551   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26552   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26553   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26554   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26567   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26568   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26569   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26570   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26571   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26582   { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26583   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26584   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26585   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26586   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26587   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26600   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26601   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26602   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26603   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26604   { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26615   { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26616   { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26617   { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26618   { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26619   { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26620   { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26633   { 964 /* buffer_load_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26634   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26635   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26636   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26637   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26638   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26657   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26658   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26659   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26660   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26661   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26662   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26675   { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26676   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26677   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26678   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26679   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26680   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26693   { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26694   { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26695   { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26696   { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26697   { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26698   { 964 /* buffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26711   { 986 /* buffer_load_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26712   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26713   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26714   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26715   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26716   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26735   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26736   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26737   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26738   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26739   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26740   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26753   { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26754   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26755   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26756   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26757   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26758   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26771   { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26772   { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26773   { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26774   { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26775   { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26776   { 986 /* buffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26789   { 1009 /* buffer_load_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26790   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26791   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26792   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26793   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26794   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26813   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26814   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26815   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26816   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26817   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26818   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26831   { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26832   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26833   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26834   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26835   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26836   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26849   { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26850   { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26851   { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26852   { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26853   { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26854   { 1009 /* buffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26867   { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26868   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26869   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26870   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26871   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26882   { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26883   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26884   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26885   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26886   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26887   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26911   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26912   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26913   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26914   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26915   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26926   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26927   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26928   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26929   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26930   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26931   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26944   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26945   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26946   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26947   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26948   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26959   { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26960   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26961   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26962   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26963   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26964   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26977   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26978   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26979   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26980   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26981   { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26992   { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26993   { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
26994   { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26995   { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26996   { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
26997   { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27202   { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27203   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27204   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27205   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27206   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27217   { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27218   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27219   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27220   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27221   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27222   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27246   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27247   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27248   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27249   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27250   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27261   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27262   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27263   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27264   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27265   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27266   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27279   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27280   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27281   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27282   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27283   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27294   { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27295   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27296   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27297   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27298   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27299   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27312   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27313   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27314   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27315   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27316   { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27327   { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27328   { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27329   { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27330   { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27331   { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27332   { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27345   { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27346   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27347   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27348   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27349   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27360   { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27361   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27362   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27363   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27364   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27365   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27389   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27390   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27391   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27392   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27393   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27404   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27405   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27406   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27407   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27408   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27409   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27422   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27423   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27424   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27425   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27426   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27437   { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27438   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27439   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27440   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27441   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27442   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27455   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27456   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27457   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27458   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27459   { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27470   { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27471   { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27472   { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27473   { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27474   { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27475   { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27584   { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27585   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27586   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27587   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27588   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27599   { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27600   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27601   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27602   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27603   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27604   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27628   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27629   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27630   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27631   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27632   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27643   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27644   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27645   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27646   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27647   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27648   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27661   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27662   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27663   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27664   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27665   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27676   { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27677   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27678   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27679   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27680   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27681   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27694   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27695   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27696   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27697   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27698   { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27709   { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27710   { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27711   { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27712   { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27713   { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27714   { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27727   { 1248 /* buffer_store_byte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27728   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27729   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27730   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27731   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27732   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27751   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27752   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27753   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27754   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27755   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27756   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27769   { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27770   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27771   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27772   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27773   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27774   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27787   { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27788   { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27789   { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27790   { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27791   { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27792   { 1248 /* buffer_store_byte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27853   { 1291 /* buffer_store_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27854   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27855   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27856   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27857   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27858   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27877   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27878   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27879   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27880   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27881   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27882   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27895   { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27896   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27897   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27898   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27899   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27900   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27913   { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27914   { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27915   { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27916   { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27917   { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27918   { 1291 /* buffer_store_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27931   { 1310 /* buffer_store_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27932   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27933   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27934   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27935   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27936   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27955   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27956   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27957   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27958   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27959   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27960   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27973   { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27974   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27975   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27976   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27977   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27978   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27991   { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27992   { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
27993   { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27994   { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27995   { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
27996   { 1310 /* buffer_store_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28009   { 1331 /* buffer_store_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28010   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28011   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28012   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28013   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28014   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28033   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28034   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28035   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28036   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28037   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28038   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28051   { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28052   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28053   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28054   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28055   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28056   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28069   { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28070   { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28071   { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28072   { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28073   { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28074   { 1331 /* buffer_store_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28087   { 1352 /* buffer_store_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28088   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28089   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28090   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28091   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28092   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28111   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28112   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28113   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28114   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28115   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28116   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28129   { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28130   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28131   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28132   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28133   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28134   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28147   { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28148   { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28149   { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28150   { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28151   { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28152   { 1352 /* buffer_store_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28477   { 1512 /* buffer_store_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28478   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28479   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28480   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28481   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28482   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28501   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28502   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28503   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28504   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28505   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28506   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28519   { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28520   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28521   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28522   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28523   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28524   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28537   { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28538   { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28539   { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28540   { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28541   { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28542   { 1512 /* buffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28555   { 1534 /* buffer_store_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28556   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28557   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28558   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28559   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28560   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28579   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28580   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28581   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28582   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28583   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28584   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28597   { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28598   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28599   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28600   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28601   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28602   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28615   { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28616   { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28617   { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28618   { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28619   { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28620   { 1534 /* buffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28633   { 1557 /* buffer_store_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28634   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28635   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28636   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28637   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28638   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28657   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28658   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28659   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28660   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28661   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28662   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28675   { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28676   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28677   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28678   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28679   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28680   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28693   { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28694   { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28695   { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28696   { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28697   { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28698   { 1557 /* buffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28711   { 1581 /* buffer_store_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28712   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28713   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28714   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28715   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28716   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28735   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28736   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28737   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28738   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28739   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28740   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28753   { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28754   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28755   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28756   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28757   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28758   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28771   { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28772   { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28773   { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28774   { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28775   { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28776   { 1581 /* buffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28793   { 1629 /* buffer_store_short */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28794   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28795   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28796   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28797   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28798   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28817   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28818   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28819   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28820   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28821   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28822   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28835   { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28836   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28837   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28838   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28839   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28840   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28853   { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28854   { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
28855   { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28856   { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28857   { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
28858   { 1629 /* buffer_store_short */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28919   { 1726 /* ds_add_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28920   { 1726 /* ds_add_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28923   { 1737 /* ds_add_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28924   { 1737 /* ds_add_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28927   { 1752 /* ds_add_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28928   { 1752 /* ds_add_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28933   { 1767 /* ds_add_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28934   { 1767 /* ds_add_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28943   { 1798 /* ds_add_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28944   { 1798 /* ds_add_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28949   { 1814 /* ds_add_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28950   { 1814 /* ds_add_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28955   { 1830 /* ds_add_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28956   { 1830 /* ds_add_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28961   { 1841 /* ds_add_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28962   { 1841 /* ds_add_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28967   { 1852 /* ds_and_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28968   { 1852 /* ds_and_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28973   { 1863 /* ds_and_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28974   { 1863 /* ds_and_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28979   { 1874 /* ds_and_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28980   { 1874 /* ds_and_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28985   { 1889 /* ds_and_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28986   { 1889 /* ds_and_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28991   { 1904 /* ds_and_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28992   { 1904 /* ds_and_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
28997   { 1920 /* ds_and_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28998   { 1920 /* ds_and_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29003   { 1936 /* ds_append */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29004   { 1936 /* ds_append */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29011   { 1962 /* ds_cmpst_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29012   { 1962 /* ds_cmpst_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29017   { 1975 /* ds_cmpst_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29018   { 1975 /* ds_cmpst_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29023   { 1988 /* ds_cmpst_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29024   { 1988 /* ds_cmpst_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29029   { 2001 /* ds_cmpst_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29030   { 2001 /* ds_cmpst_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29035   { 2014 /* ds_cmpst_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29036   { 2014 /* ds_cmpst_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29041   { 2031 /* ds_cmpst_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29042   { 2031 /* ds_cmpst_rtn_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29047   { 2048 /* ds_cmpst_rtn_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29048   { 2048 /* ds_cmpst_rtn_f32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29053   { 2065 /* ds_cmpst_rtn_f64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29054   { 2065 /* ds_cmpst_rtn_f64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29065   { 2104 /* ds_consume */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29066   { 2104 /* ds_consume */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29071   { 2115 /* ds_dec_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29072   { 2115 /* ds_dec_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29077   { 2130 /* ds_dec_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29078   { 2130 /* ds_dec_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29083   { 2145 /* ds_dec_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29084   { 2145 /* ds_dec_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29089   { 2161 /* ds_dec_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29090   { 2161 /* ds_dec_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29095   { 2177 /* ds_dec_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29096   { 2177 /* ds_dec_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29101   { 2188 /* ds_dec_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29102   { 2188 /* ds_dec_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29107   { 2199 /* ds_gws_barrier */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29110   { 2214 /* ds_gws_init */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29113   { 2226 /* ds_gws_sema_br */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29116   { 2241 /* ds_gws_sema_p */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29122   { 2279 /* ds_gws_sema_v */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29125   { 2293 /* ds_inc_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29126   { 2293 /* ds_inc_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29131   { 2308 /* ds_inc_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29132   { 2308 /* ds_inc_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29137   { 2323 /* ds_inc_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29138   { 2323 /* ds_inc_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29143   { 2339 /* ds_inc_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29144   { 2339 /* ds_inc_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29149   { 2355 /* ds_inc_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29150   { 2355 /* ds_inc_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29155   { 2366 /* ds_inc_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29156   { 2366 /* ds_inc_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29161   { 2377 /* ds_max_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29162   { 2377 /* ds_max_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29167   { 2388 /* ds_max_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29168   { 2388 /* ds_max_f64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29173   { 2399 /* ds_max_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29174   { 2399 /* ds_max_i32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29179   { 2410 /* ds_max_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29180   { 2410 /* ds_max_i64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29185   { 2421 /* ds_max_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29186   { 2421 /* ds_max_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29191   { 2436 /* ds_max_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29192   { 2436 /* ds_max_rtn_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29197   { 2451 /* ds_max_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29198   { 2451 /* ds_max_rtn_i32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29203   { 2466 /* ds_max_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29204   { 2466 /* ds_max_rtn_i64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29209   { 2481 /* ds_max_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29210   { 2481 /* ds_max_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29215   { 2496 /* ds_max_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29216   { 2496 /* ds_max_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29221   { 2511 /* ds_max_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29222   { 2511 /* ds_max_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29227   { 2527 /* ds_max_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29228   { 2527 /* ds_max_src2_f64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29233   { 2543 /* ds_max_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29234   { 2543 /* ds_max_src2_i32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29239   { 2559 /* ds_max_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29240   { 2559 /* ds_max_src2_i64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29245   { 2575 /* ds_max_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29246   { 2575 /* ds_max_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29251   { 2591 /* ds_max_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29252   { 2591 /* ds_max_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29257   { 2607 /* ds_max_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29258   { 2607 /* ds_max_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29263   { 2618 /* ds_max_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29264   { 2618 /* ds_max_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29269   { 2629 /* ds_min_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29270   { 2629 /* ds_min_f32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29275   { 2640 /* ds_min_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29276   { 2640 /* ds_min_f64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29281   { 2651 /* ds_min_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29282   { 2651 /* ds_min_i32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29287   { 2662 /* ds_min_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29288   { 2662 /* ds_min_i64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29293   { 2673 /* ds_min_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29294   { 2673 /* ds_min_rtn_f32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29299   { 2688 /* ds_min_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29300   { 2688 /* ds_min_rtn_f64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29305   { 2703 /* ds_min_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29306   { 2703 /* ds_min_rtn_i32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29311   { 2718 /* ds_min_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29312   { 2718 /* ds_min_rtn_i64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29317   { 2733 /* ds_min_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29318   { 2733 /* ds_min_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29323   { 2748 /* ds_min_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29324   { 2748 /* ds_min_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29329   { 2763 /* ds_min_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29330   { 2763 /* ds_min_src2_f32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29335   { 2779 /* ds_min_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29336   { 2779 /* ds_min_src2_f64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29341   { 2795 /* ds_min_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29342   { 2795 /* ds_min_src2_i32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29347   { 2811 /* ds_min_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29348   { 2811 /* ds_min_src2_i64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29353   { 2827 /* ds_min_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29354   { 2827 /* ds_min_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29359   { 2843 /* ds_min_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29360   { 2843 /* ds_min_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29365   { 2859 /* ds_min_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29366   { 2859 /* ds_min_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29371   { 2870 /* ds_min_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29372   { 2870 /* ds_min_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29377   { 2881 /* ds_mskor_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29378   { 2881 /* ds_mskor_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29383   { 2894 /* ds_mskor_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29384   { 2894 /* ds_mskor_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29389   { 2907 /* ds_mskor_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29390   { 2907 /* ds_mskor_rtn_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29395   { 2924 /* ds_mskor_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29396   { 2924 /* ds_mskor_rtn_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29401   { 2948 /* ds_or_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29402   { 2948 /* ds_or_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29407   { 2958 /* ds_or_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29408   { 2958 /* ds_or_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29413   { 2968 /* ds_or_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29414   { 2968 /* ds_or_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29419   { 2982 /* ds_or_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29420   { 2982 /* ds_or_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29425   { 2996 /* ds_or_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29426   { 2996 /* ds_or_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29431   { 3011 /* ds_or_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29432   { 3011 /* ds_or_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29437   { 3026 /* ds_ordered_count */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29442   { 3058 /* ds_read2_b32 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29443   { 3058 /* ds_read2_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29444   { 3058 /* ds_read2_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29451   { 3071 /* ds_read2_b64 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29452   { 3071 /* ds_read2_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29453   { 3071 /* ds_read2_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29460   { 3084 /* ds_read2st64_b32 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29461   { 3084 /* ds_read2st64_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29462   { 3084 /* ds_read2st64_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29469   { 3101 /* ds_read2st64_b64 */, 4 /* 2 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29470   { 3101 /* ds_read2st64_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29471   { 3101 /* ds_read2st64_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29488   { 3150 /* ds_read_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29489   { 3150 /* ds_read_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29494   { 3162 /* ds_read_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29495   { 3162 /* ds_read_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29506   { 3186 /* ds_read_i16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29507   { 3186 /* ds_read_i16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29512   { 3198 /* ds_read_i8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29513   { 3198 /* ds_read_i8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29526   { 3242 /* ds_read_u16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29527   { 3242 /* ds_read_u16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29540   { 3289 /* ds_read_u8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29541   { 3289 /* ds_read_u8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29554   { 3333 /* ds_rsub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29555   { 3333 /* ds_rsub_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29560   { 3349 /* ds_rsub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29561   { 3349 /* ds_rsub_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29566   { 3365 /* ds_rsub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29567   { 3365 /* ds_rsub_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29572   { 3382 /* ds_rsub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29573   { 3382 /* ds_rsub_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29578   { 3399 /* ds_rsub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29579   { 3399 /* ds_rsub_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29584   { 3411 /* ds_rsub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29585   { 3411 /* ds_rsub_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29590   { 3423 /* ds_sub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29591   { 3423 /* ds_sub_rtn_u32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29596   { 3438 /* ds_sub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29597   { 3438 /* ds_sub_rtn_u64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29602   { 3453 /* ds_sub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29603   { 3453 /* ds_sub_src2_u32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29608   { 3469 /* ds_sub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29609   { 3469 /* ds_sub_src2_u64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29614   { 3485 /* ds_sub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29615   { 3485 /* ds_sub_u32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29620   { 3496 /* ds_sub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29621   { 3496 /* ds_sub_u64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29626   { 3507 /* ds_swizzle_b32 */, 4 /* 2 */, MCK_Swizzle, AMFBS_isGFX10Plus },
29627   { 3507 /* ds_swizzle_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29638   { 3538 /* ds_write2_b32 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29639   { 3538 /* ds_write2_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29640   { 3538 /* ds_write2_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29647   { 3552 /* ds_write2_b64 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29648   { 3552 /* ds_write2_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29649   { 3552 /* ds_write2_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29656   { 3566 /* ds_write2st64_b32 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29657   { 3566 /* ds_write2st64_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29658   { 3566 /* ds_write2st64_b32 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29665   { 3584 /* ds_write2st64_b64 */, 8 /* 3 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29666   { 3584 /* ds_write2st64_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29667   { 3584 /* ds_write2st64_b64 */, 32 /* 5 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29684   { 3636 /* ds_write_b16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29685   { 3636 /* ds_write_b16 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29694   { 3669 /* ds_write_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29695   { 3669 /* ds_write_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29700   { 3682 /* ds_write_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29701   { 3682 /* ds_write_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29706   { 3695 /* ds_write_b8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29707   { 3695 /* ds_write_b8 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29722   { 3739 /* ds_write_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29723   { 3739 /* ds_write_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29728   { 3757 /* ds_write_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29729   { 3757 /* ds_write_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29734   { 3775 /* ds_wrxchg2_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29735   { 3775 /* ds_wrxchg2_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29736   { 3775 /* ds_wrxchg2_rtn_b32 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29743   { 3794 /* ds_wrxchg2_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29744   { 3794 /* ds_wrxchg2_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29745   { 3794 /* ds_wrxchg2_rtn_b64 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29752   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29753   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29754   { 3813 /* ds_wrxchg2st64_rtn_b32 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29761   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset0, AMFBS_isGFX10Plus },
29762   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29763   { 3836 /* ds_wrxchg2st64_rtn_b64 */, 64 /* 6 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29770   { 3859 /* ds_wrxchg_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29771   { 3859 /* ds_wrxchg_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29776   { 3877 /* ds_wrxchg_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29777   { 3877 /* ds_wrxchg_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29782   { 3895 /* ds_xor_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29783   { 3895 /* ds_xor_b32 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29788   { 3906 /* ds_xor_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29789   { 3906 /* ds_xor_b64 */, 8 /* 3 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29794   { 3917 /* ds_xor_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29795   { 3917 /* ds_xor_rtn_b32 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29800   { 3932 /* ds_xor_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29801   { 3932 /* ds_xor_rtn_b64 */, 16 /* 4 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29806   { 3947 /* ds_xor_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29807   { 3947 /* ds_xor_src2_b32 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29812   { 3963 /* ds_xor_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29813   { 3963 /* ds_xor_src2_b64 */, 4 /* 2 */, MCK_ImmGDS, AMFBS_isGFX10Plus },
29818   { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX10Plus },
29819   { 3979 /* exp */, 32 /* 5 */, MCK_ImmExpCompr, AMFBS_isGFX10Plus },
29820   { 3979 /* exp */, 64 /* 6 */, MCK_ImmExpVM, AMFBS_isGFX10Plus },
29821   { 3979 /* exp */, 1 /* 0 */, MCK_ImmExpTgt, AMFBS_isGFX10Plus },
29830   { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX10Plus },
29831   { 3979 /* exp */, 64 /* 6 */, MCK_ImmExpCompr, AMFBS_isGFX10Plus },
29832   { 3979 /* exp */, 128 /* 7 */, MCK_ImmExpVM, AMFBS_isGFX10Plus },
29833   { 3979 /* exp */, 1 /* 0 */, MCK_ImmExpTgt, AMFBS_isGFX10Plus },
70751   { 9380 /* s_buffer_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70752   { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70760   { 9380 /* s_buffer_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70761   { 9380 /* s_buffer_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70762   { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70769   { 9400 /* s_buffer_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70770   { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70778   { 9400 /* s_buffer_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70779   { 9400 /* s_buffer_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70780   { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70787   { 9423 /* s_buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70788   { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70796   { 9423 /* s_buffer_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70797   { 9423 /* s_buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70798   { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70805   { 9445 /* s_buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70806   { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70814   { 9445 /* s_buffer_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70815   { 9445 /* s_buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70816   { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70823   { 9467 /* s_buffer_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70824   { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70832   { 9467 /* s_buffer_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70833   { 9467 /* s_buffer_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70834   { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70900   { 10559 /* s_getreg_b32 */, 2 /* 1 */, MCK_ImmHwreg, AMFBS_isGFX10Plus },
70903   { 10626 /* s_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70904   { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70912   { 10626 /* s_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70913   { 10626 /* s_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70914   { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70921   { 10639 /* s_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70922   { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70930   { 10639 /* s_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70931   { 10639 /* s_load_dwordx16 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70932   { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70939   { 10655 /* s_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70940   { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70948   { 10655 /* s_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70949   { 10655 /* s_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70950   { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70957   { 10670 /* s_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70958   { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70966   { 10670 /* s_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70967   { 10670 /* s_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70968   { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70975   { 10685 /* s_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70976   { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70984   { 10685 /* s_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_isGFX10Plus },
70985   { 10685 /* s_load_dwordx8 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
70986   { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71057   { 11755 /* s_setreg_b32 */, 1 /* 0 */, MCK_ImmHwreg, AMFBS_isGFX10Plus },
71060   { 11768 /* s_setreg_imm32_b32 */, 1 /* 0 */, MCK_ImmHwreg, AMFBS_isGFX10Plus },
71784   { 12866 /* tbuffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71785   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71786   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71787   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71788   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71789   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71790   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71812   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71813   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71814   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71815   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71816   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71817   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71818   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71833   { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71834   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71835   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71836   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71837   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71838   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71839   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71854   { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71855   { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71856   { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71857   { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71858   { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71859   { 12866 /* tbuffer_load_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71860   { 12866 /* tbuffer_load_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71875   { 12888 /* tbuffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71876   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71877   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71878   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71879   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71880   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71881   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71903   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71904   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71905   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71906   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71907   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71908   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71909   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71924   { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71925   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71926   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71927   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71928   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71929   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71930   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71945   { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71946   { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71947   { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71948   { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71949   { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71950   { 12888 /* tbuffer_load_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71951   { 12888 /* tbuffer_load_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71966   { 12911 /* tbuffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71967   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71968   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71969   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71970   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71971   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71972   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
71994   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71995   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
71996   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71997   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71998   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
71999   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72000   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72015   { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72016   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72017   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72018   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72019   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72020   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72021   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72036   { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72037   { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72038   { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72039   { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72040   { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72041   { 12911 /* tbuffer_load_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72042   { 12911 /* tbuffer_load_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72057   { 12935 /* tbuffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72058   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72059   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72060   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72061   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72062   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72063   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72085   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72086   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72087   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72088   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72089   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72090   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72091   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72106   { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72107   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72108   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72109   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72110   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72111   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72112   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72127   { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72128   { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72129   { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72130   { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72131   { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72132   { 12935 /* tbuffer_load_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72133   { 12935 /* tbuffer_load_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72484   { 13074 /* tbuffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72485   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72486   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72487   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72488   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72489   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72490   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72512   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72513   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72514   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72515   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72516   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72517   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72518   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72533   { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72534   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72535   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72536   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72537   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72538   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72539   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72554   { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72555   { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72556   { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72557   { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72558   { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72559   { 13074 /* tbuffer_store_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72560   { 13074 /* tbuffer_store_format_x */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72575   { 13097 /* tbuffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72576   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72577   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72578   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72579   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72580   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72581   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72603   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72604   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72605   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72606   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72607   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72608   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72609   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72624   { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72625   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72626   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72627   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72628   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72629   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72630   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72645   { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72646   { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72647   { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72648   { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72649   { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72650   { 13097 /* tbuffer_store_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72651   { 13097 /* tbuffer_store_format_xy */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72666   { 13121 /* tbuffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72667   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72668   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72669   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72670   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72671   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72672   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72694   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72695   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72696   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72697   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72698   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72699   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72700   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72715   { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72716   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72717   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72718   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72719   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72720   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72721   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72736   { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72737   { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72738   { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72739   { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72740   { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72741   { 13121 /* tbuffer_store_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72742   { 13121 /* tbuffer_store_format_xyz */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72757   { 13146 /* tbuffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72758   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72759   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72760   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72761   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72762   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72763   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72785   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72786   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72787   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72788   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72789   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72790   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72791   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72806   { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72807   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72808   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72809   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72810   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72811   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72812   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72827   { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72828   { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmDLC, AMFBS_isGFX10Plus },
72829   { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72830   { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72831   { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmTFE, AMFBS_isGFX10Plus },
72832   { 13146 /* tbuffer_store_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72833   { 13146 /* tbuffer_store_format_xyzw */, 8 /* 3 */, MCK_ImmFORMAT, AMFBS_isGFX10Plus },
72850   { 13222 /* v_add_co_ci_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX10Plus },
72851   { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72889   { 13238 /* v_add_co_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX10Plus },
72890   { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72944   { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
72945   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
72946   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72984   { 13271 /* v_add_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
72985   { 13271 /* v_add_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
72986   { 13271 /* v_add_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73216   { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73217   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
73218   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73281   { 13677 /* v_cmp_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73282   { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73302   { 13713 /* v_cmp_class_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73303   { 13713 /* v_cmp_class_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73326   { 13779 /* v_cmp_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73327   { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73328   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73347   { 13809 /* v_cmp_eq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73348   { 13809 /* v_cmp_eq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73349   { 13809 /* v_cmp_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73370   { 13869 /* v_cmp_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73385   { 13899 /* v_cmp_eq_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73402   { 13959 /* v_cmp_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73417   { 13989 /* v_cmp_eq_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73438   { 14047 /* v_cmp_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73439   { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73440   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73459   { 14075 /* v_cmp_f_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73460   { 14075 /* v_cmp_f_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73461   { 14075 /* v_cmp_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73477   { 14131 /* v_cmp_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73492   { 14159 /* v_cmp_f_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73504   { 14215 /* v_cmp_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73519   { 14243 /* v_cmp_f_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73540   { 14301 /* v_cmp_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73541   { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73542   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73561   { 14331 /* v_cmp_ge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73562   { 14331 /* v_cmp_ge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73563   { 14331 /* v_cmp_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73584   { 14391 /* v_cmp_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73599   { 14421 /* v_cmp_ge_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73616   { 14481 /* v_cmp_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73631   { 14511 /* v_cmp_ge_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73652   { 14571 /* v_cmp_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73653   { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73654   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73673   { 14601 /* v_cmp_gt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73674   { 14601 /* v_cmp_gt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73675   { 14601 /* v_cmp_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73696   { 14661 /* v_cmp_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73711   { 14691 /* v_cmp_gt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73728   { 14751 /* v_cmp_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73743   { 14781 /* v_cmp_gt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73764   { 14841 /* v_cmp_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73765   { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73766   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73785   { 14871 /* v_cmp_le_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73786   { 14871 /* v_cmp_le_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73787   { 14871 /* v_cmp_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73808   { 14931 /* v_cmp_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73823   { 14961 /* v_cmp_le_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73840   { 15021 /* v_cmp_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73855   { 15051 /* v_cmp_le_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73876   { 15111 /* v_cmp_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73877   { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73878   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73897   { 15141 /* v_cmp_lg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73898   { 15141 /* v_cmp_lg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73899   { 15141 /* v_cmp_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73924   { 15201 /* v_cmp_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73925   { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
73926   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73945   { 15231 /* v_cmp_lt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73946   { 15231 /* v_cmp_lt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
73947   { 15231 /* v_cmp_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73968   { 15291 /* v_cmp_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
73983   { 15321 /* v_cmp_lt_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74000   { 15381 /* v_cmp_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74015   { 15411 /* v_cmp_lt_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74032   { 15471 /* v_cmp_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74047   { 15501 /* v_cmp_ne_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74064   { 15561 /* v_cmp_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74079   { 15591 /* v_cmp_ne_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74100   { 15653 /* v_cmp_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74101   { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74102   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74121   { 15685 /* v_cmp_neq_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74122   { 15685 /* v_cmp_neq_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74123   { 15685 /* v_cmp_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74148   { 15749 /* v_cmp_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74149   { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74150   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74169   { 15781 /* v_cmp_nge_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74170   { 15781 /* v_cmp_nge_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74171   { 15781 /* v_cmp_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74196   { 15845 /* v_cmp_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74197   { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74198   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74217   { 15877 /* v_cmp_ngt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74218   { 15877 /* v_cmp_ngt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74219   { 15877 /* v_cmp_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74244   { 15941 /* v_cmp_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74245   { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74246   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74265   { 15973 /* v_cmp_nle_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74266   { 15973 /* v_cmp_nle_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74267   { 15973 /* v_cmp_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74292   { 16037 /* v_cmp_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74293   { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74294   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74313   { 16069 /* v_cmp_nlg_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74314   { 16069 /* v_cmp_nlg_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74315   { 16069 /* v_cmp_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74340   { 16133 /* v_cmp_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74341   { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74342   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74361   { 16165 /* v_cmp_nlt_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74362   { 16165 /* v_cmp_nlt_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74363   { 16165 /* v_cmp_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74388   { 16225 /* v_cmp_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74389   { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74390   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74409   { 16253 /* v_cmp_o_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74410   { 16253 /* v_cmp_o_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74411   { 16253 /* v_cmp_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74427   { 16309 /* v_cmp_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74442   { 16337 /* v_cmp_t_i64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74454   { 16393 /* v_cmp_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74469   { 16421 /* v_cmp_t_u64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74490   { 16481 /* v_cmp_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74491   { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74492   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74511   { 16513 /* v_cmp_tru_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74512   { 16513 /* v_cmp_tru_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74513   { 16513 /* v_cmp_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74538   { 16573 /* v_cmp_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74539   { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
74540   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74559   { 16601 /* v_cmp_u_f64 */, 1 /* 0 */, MCK_BoolReg, AMFBS_isGFX10Plus },
74560   { 16601 /* v_cmp_u_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
74561   { 16601 /* v_cmp_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
75909   { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_BoolReg, AMFBS_isGFX10Plus },
75910   { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76008   { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76009   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76010   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76045   { 21993 /* v_cubeid_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76046   { 21993 /* v_cubeid_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76047   { 21993 /* v_cubeid_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76054   { 22006 /* v_cubema_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76055   { 22006 /* v_cubema_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76056   { 22006 /* v_cubema_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76063   { 22019 /* v_cubesc_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76064   { 22019 /* v_cubesc_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76065   { 22019 /* v_cubesc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76072   { 22032 /* v_cubetc_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76073   { 22032 /* v_cubetc_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76074   { 22032 /* v_cubetc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76083   { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76084   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76085   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76186   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX10Plus },
76187   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76188   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76223   { 22101 /* v_cvt_f32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
76224   { 22101 /* v_cvt_f32_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76225   { 22101 /* v_cvt_f32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76234   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76235   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76268   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76269   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76302   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76303   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76336   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76337   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76370   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76371   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76404   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76405   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76436   { 22211 /* v_cvt_f64_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76437   { 22211 /* v_cvt_f64_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76438   { 22211 /* v_cvt_f64_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76445   { 22225 /* v_cvt_f64_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76446   { 22225 /* v_cvt_f64_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76451   { 22239 /* v_cvt_f64_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76452   { 22239 /* v_cvt_f64_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76457   { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76458   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76523   { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76524   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76557   { 22299 /* v_cvt_i32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
76558   { 22299 /* v_cvt_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76629   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76630   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76661   { 22402 /* v_cvt_pk_u8_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76662   { 22402 /* v_cvt_pk_u8_f32 */, 12 /* 2, 3 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus },
76663   { 22402 /* v_cvt_pk_u8_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76682   { 22460 /* v_cvt_pknorm_i16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76683   { 22460 /* v_cvt_pknorm_i16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76694   { 22502 /* v_cvt_pknorm_u16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76695   { 22502 /* v_cvt_pknorm_u16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76700   { 22523 /* v_cvt_pkrtz_f16_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76701   { 22523 /* v_cvt_pkrtz_f16_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76702   { 22523 /* v_cvt_pkrtz_f16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76709   { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76710   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76775   { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76776   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76809   { 22589 /* v_cvt_u32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
76810   { 22589 /* v_cvt_u32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76818   { 22603 /* v_div_fixup_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX10Plus },
76819   { 22603 /* v_div_fixup_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76820   { 22603 /* v_div_fixup_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
76824   { 22619 /* v_div_fixup_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76825   { 22619 /* v_div_fixup_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76826   { 22619 /* v_div_fixup_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76833   { 22635 /* v_div_fixup_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
76834   { 22635 /* v_div_fixup_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76835   { 22635 /* v_div_fixup_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76845   { 22674 /* v_div_fmas_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
76846   { 22674 /* v_div_fmas_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76847   { 22674 /* v_div_fmas_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76854   { 22689 /* v_div_fmas_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
76855   { 22689 /* v_div_fmas_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
76856   { 22689 /* v_div_fmas_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76863   { 22704 /* v_div_scale_f32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX10Plus },
76866   { 22720 /* v_div_scale_f64 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX10Plus },
77013   { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77014   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77015   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77188   { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77189   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77190   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77237   { 23005 /* v_fma_f16 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP16InputMods, AMFBS_isGFX10Plus },
77238   { 23005 /* v_fma_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77239   { 23005 /* v_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
77243   { 23015 /* v_fma_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77244   { 23015 /* v_fma_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77245   { 23015 /* v_fma_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77252   { 23025 /* v_fma_f64 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
77253   { 23025 /* v_fma_f64 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77254   { 23025 /* v_fma_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77366   { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77367   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77368   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77403   { 23192 /* v_fract_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
77404   { 23192 /* v_fract_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77405   { 23192 /* v_fract_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77444   { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77445   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77478   { 23244 /* v_frexp_exp_i32_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
77479   { 23244 /* v_frexp_exp_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77522   { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77523   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77524   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77559   { 23298 /* v_frexp_mant_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
77560   { 23298 /* v_frexp_mant_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77561   { 23298 /* v_frexp_mant_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77568   { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77569   { 23315 /* v_interp_mov_f32 */, 2 /* 1 */, MCK_InterpSlot, AMFBS_isGFX10Plus },
77582   { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77585   { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77630   { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77691   { 23451 /* v_ldexp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77692   { 23451 /* v_ldexp_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus },
77693   { 23451 /* v_ldexp_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77694   { 23451 /* v_ldexp_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77703   { 23463 /* v_ldexp_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
77704   { 23463 /* v_ldexp_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus },
77705   { 23463 /* v_ldexp_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77706   { 23463 /* v_ldexp_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77756   { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77757   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77758   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77921   { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77922   { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77923   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77974   { 23742 /* v_mad_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
77975   { 23742 /* v_mad_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
77976   { 23742 /* v_mad_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77992   { 23776 /* v_mad_i32_i24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78004   { 23821 /* v_mad_legacy_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78005   { 23821 /* v_mad_legacy_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78006   { 23821 /* v_mad_legacy_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78036   { 23942 /* v_mad_u32_u24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78046   { 23982 /* v_madak_f32 */, 8 /* 3 */, MCK_KImmFP32, AMFBS_isGFX10Plus },
78050   { 24006 /* v_madmk_f32 */, 4 /* 2 */, MCK_KImmFP32, AMFBS_isGFX10Plus },
78059   { 24029 /* v_max3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78060   { 24029 /* v_max3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78061   { 24029 /* v_max3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78117   { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78118   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78119   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78157   { 24104 /* v_max_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
78158   { 24104 /* v_max_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78159   { 24104 /* v_max_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78265   { 24220 /* v_med3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78266   { 24220 /* v_med3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78267   { 24220 /* v_med3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78348   { 24720 /* v_min3_f32 */, 14 /* 1, 2, 3 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78349   { 24720 /* v_min3_f32 */, 32 /* 5 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78350   { 24720 /* v_min3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78406   { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78407   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78408   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78446   { 24795 /* v_min_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
78447   { 24795 /* v_min_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78448   { 24795 /* v_min_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78600   { 24946 /* v_mqsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78606   { 24979 /* v_msad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78650   { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78651   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78652   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78690   { 25009 /* v_mul_f64 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
78691   { 25009 /* v_mul_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78692   { 25009 /* v_mul_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78788   { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
78789   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
78790   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78942   { 25284 /* v_pk_add_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78943   { 25284 /* v_pk_add_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78944   { 25284 /* v_pk_add_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
78945   { 25284 /* v_pk_add_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
78946   { 25284 /* v_pk_add_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
78952   { 25297 /* v_pk_add_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78953   { 25297 /* v_pk_add_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78954   { 25297 /* v_pk_add_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
78955   { 25297 /* v_pk_add_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
78956   { 25297 /* v_pk_add_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
78962   { 25310 /* v_pk_add_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78963   { 25310 /* v_pk_add_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78964   { 25310 /* v_pk_add_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
78965   { 25310 /* v_pk_add_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
78966   { 25310 /* v_pk_add_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
78972   { 25323 /* v_pk_ashrrev_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78973   { 25323 /* v_pk_ashrrev_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78974   { 25323 /* v_pk_ashrrev_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
78975   { 25323 /* v_pk_ashrrev_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
78976   { 25323 /* v_pk_ashrrev_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
78982   { 25340 /* v_pk_fma_f16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78983   { 25340 /* v_pk_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78984   { 25340 /* v_pk_fma_f16 */, 32 /* 5 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
78985   { 25340 /* v_pk_fma_f16 */, 64 /* 6 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
78986   { 25340 /* v_pk_fma_f16 */, 128 /* 7 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
78992   { 25367 /* v_pk_lshlrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78993   { 25367 /* v_pk_lshlrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78994   { 25367 /* v_pk_lshlrev_b16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
78995   { 25367 /* v_pk_lshlrev_b16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
78996   { 25367 /* v_pk_lshlrev_b16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79002   { 25384 /* v_pk_lshrrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79003   { 25384 /* v_pk_lshrrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79004   { 25384 /* v_pk_lshrrev_b16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79005   { 25384 /* v_pk_lshrrev_b16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79006   { 25384 /* v_pk_lshrrev_b16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79012   { 25401 /* v_pk_mad_i16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79013   { 25401 /* v_pk_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79014   { 25401 /* v_pk_mad_i16 */, 32 /* 5 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79015   { 25401 /* v_pk_mad_i16 */, 64 /* 6 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79016   { 25401 /* v_pk_mad_i16 */, 128 /* 7 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79022   { 25414 /* v_pk_mad_u16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79023   { 25414 /* v_pk_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79024   { 25414 /* v_pk_mad_u16 */, 32 /* 5 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79025   { 25414 /* v_pk_mad_u16 */, 64 /* 6 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79026   { 25414 /* v_pk_mad_u16 */, 128 /* 7 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79032   { 25427 /* v_pk_max_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79033   { 25427 /* v_pk_max_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79034   { 25427 /* v_pk_max_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79035   { 25427 /* v_pk_max_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79036   { 25427 /* v_pk_max_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79042   { 25440 /* v_pk_max_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79043   { 25440 /* v_pk_max_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79044   { 25440 /* v_pk_max_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79045   { 25440 /* v_pk_max_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79046   { 25440 /* v_pk_max_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79052   { 25453 /* v_pk_max_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79053   { 25453 /* v_pk_max_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79054   { 25453 /* v_pk_max_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79055   { 25453 /* v_pk_max_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79056   { 25453 /* v_pk_max_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79062   { 25466 /* v_pk_min_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79063   { 25466 /* v_pk_min_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79064   { 25466 /* v_pk_min_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79065   { 25466 /* v_pk_min_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79066   { 25466 /* v_pk_min_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79072   { 25479 /* v_pk_min_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79073   { 25479 /* v_pk_min_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79074   { 25479 /* v_pk_min_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79075   { 25479 /* v_pk_min_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79076   { 25479 /* v_pk_min_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79082   { 25492 /* v_pk_min_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79083   { 25492 /* v_pk_min_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79084   { 25492 /* v_pk_min_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79085   { 25492 /* v_pk_min_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79086   { 25492 /* v_pk_min_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79092   { 25505 /* v_pk_mul_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79093   { 25505 /* v_pk_mul_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79094   { 25505 /* v_pk_mul_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79095   { 25505 /* v_pk_mul_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79096   { 25505 /* v_pk_mul_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79102   { 25518 /* v_pk_mul_lo_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79103   { 25518 /* v_pk_mul_lo_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79104   { 25518 /* v_pk_mul_lo_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79105   { 25518 /* v_pk_mul_lo_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79106   { 25518 /* v_pk_mul_lo_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79112   { 25534 /* v_pk_sub_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79113   { 25534 /* v_pk_sub_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79114   { 25534 /* v_pk_sub_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79115   { 25534 /* v_pk_sub_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79116   { 25534 /* v_pk_sub_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79122   { 25547 /* v_pk_sub_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79123   { 25547 /* v_pk_sub_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79124   { 25547 /* v_pk_sub_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_isGFX10Plus },
79125   { 25547 /* v_pk_sub_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_isGFX10Plus },
79126   { 25547 /* v_pk_sub_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_isGFX10Plus },
79179   { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79180   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79181   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79216   { 25629 /* v_rcp_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
79217   { 25629 /* v_rcp_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79218   { 25629 /* v_rcp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79227   { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79228   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79229   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79305   { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79306   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79307   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79395   { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79396   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79397   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79432   { 25795 /* v_rsq_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
79433   { 25795 /* v_rsq_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79434   { 25795 /* v_rsq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79444   { 25822 /* v_sad_hi_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79447   { 25834 /* v_sad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79450   { 25844 /* v_sad_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79453   { 25854 /* v_sad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79529   { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79530   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79531   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79604   { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79605   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79606   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79641   { 25948 /* v_sqrt_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
79642   { 25948 /* v_sqrt_f64 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79643   { 25948 /* v_sqrt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79652   { 25959 /* v_sub_co_ci_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX10Plus },
79653   { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79691   { 25975 /* v_sub_co_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX10Plus },
79692   { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79746   { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79747   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79748   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79899   { 26156 /* v_subrev_co_ci_u32 */, 18 /* 1, 4 */, MCK_BoolReg, AMFBS_isGFX10Plus },
79900   { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79938   { 26175 /* v_subrev_co_u32 */, 2 /* 1 */, MCK_BoolReg, AMFBS_isGFX10Plus },
79939   { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79993   { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
79994   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
79995   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
80088   { 26297 /* v_trig_preop_f64 */, 2 /* 1 */, MCK_RegOrImmWithFP64InputMods, AMFBS_isGFX10Plus },
80089   { 26297 /* v_trig_preop_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus },
80090   { 26297 /* v_trig_preop_f64 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
80091   { 26297 /* v_trig_preop_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
80138   { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_RegOrImmWithFP32InputMods, AMFBS_isGFX10Plus },
80139   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_isGFX10Plus },
80140   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },