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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12417 { 1674 /* buffer_wbinvl1 */, AMDGPU::BUFFER_WBINVL1_gfx6_gfx7, Convert_NoOperands, AMFBS_None, { }, },
17810 { 8505 /* s_barrier */, AMDGPU::S_BARRIER, Convert_NoOperands, AMFBS_None, { }, },
17841 { 8639 /* s_bitcmp0_b32 */, AMDGPU::S_BITCMP0_B32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
17842 { 8653 /* s_bitcmp0_b64 */, AMDGPU::S_BITCMP0_B64, Convert__SSrcB641_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB64, MCK_SSrcB32 }, },
17843 { 8667 /* s_bitcmp1_b32 */, AMDGPU::S_BITCMP1_B32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
17844 { 8681 /* s_bitcmp1_b64 */, AMDGPU::S_BITCMP1_B64, Convert__SSrcB641_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB64, MCK_SSrcB32 }, },
17859 { 8774 /* s_branch */, AMDGPU::S_BRANCH, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
17860 { 8774 /* s_branch */, AMDGPU::S_BRANCH_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18124 { 9567 /* s_cbranch_cdbgsys */, AMDGPU::S_CBRANCH_CDBGSYS, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18125 { 9567 /* s_cbranch_cdbgsys */, AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18126 { 9585 /* s_cbranch_cdbgsys_and_user */, AMDGPU::S_CBRANCH_CDBGSYS_AND_USER, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18127 { 9585 /* s_cbranch_cdbgsys_and_user */, AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18128 { 9612 /* s_cbranch_cdbgsys_or_user */, AMDGPU::S_CBRANCH_CDBGSYS_OR_USER, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18129 { 9612 /* s_cbranch_cdbgsys_or_user */, AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18130 { 9638 /* s_cbranch_cdbguser */, AMDGPU::S_CBRANCH_CDBGUSER, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18131 { 9638 /* s_cbranch_cdbguser */, AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18132 { 9657 /* s_cbranch_execnz */, AMDGPU::S_CBRANCH_EXECNZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18133 { 9657 /* s_cbranch_execnz */, AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18134 { 9674 /* s_cbranch_execz */, AMDGPU::S_CBRANCH_EXECZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18135 { 9674 /* s_cbranch_execz */, AMDGPU::S_CBRANCH_EXECZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18142 { 9739 /* s_cbranch_scc0 */, AMDGPU::S_CBRANCH_SCC0, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18143 { 9739 /* s_cbranch_scc0 */, AMDGPU::S_CBRANCH_SCC0_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18144 { 9754 /* s_cbranch_scc1 */, AMDGPU::S_CBRANCH_SCC1, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18145 { 9754 /* s_cbranch_scc1 */, AMDGPU::S_CBRANCH_SCC1_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18146 { 9769 /* s_cbranch_vccnz */, AMDGPU::S_CBRANCH_VCCNZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18147 { 9769 /* s_cbranch_vccnz */, AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18148 { 9785 /* s_cbranch_vccz */, AMDGPU::S_CBRANCH_VCCZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18149 { 9785 /* s_cbranch_vccz */, AMDGPU::S_CBRANCH_VCCZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18160 { 9843 /* s_cmp_eq_i32 */, AMDGPU::S_CMP_EQ_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18161 { 9856 /* s_cmp_eq_u32 */, AMDGPU::S_CMP_EQ_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18163 { 9882 /* s_cmp_ge_i32 */, AMDGPU::S_CMP_GE_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18164 { 9895 /* s_cmp_ge_u32 */, AMDGPU::S_CMP_GE_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18165 { 9908 /* s_cmp_gt_i32 */, AMDGPU::S_CMP_GT_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18166 { 9921 /* s_cmp_gt_u32 */, AMDGPU::S_CMP_GT_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18167 { 9934 /* s_cmp_le_i32 */, AMDGPU::S_CMP_LE_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18168 { 9947 /* s_cmp_le_u32 */, AMDGPU::S_CMP_LE_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18169 { 9960 /* s_cmp_lg_i32 */, AMDGPU::S_CMP_LG_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18170 { 9973 /* s_cmp_lg_u32 */, AMDGPU::S_CMP_LG_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18172 { 9999 /* s_cmp_lt_i32 */, AMDGPU::S_CMP_LT_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18173 { 10012 /* s_cmp_lt_u32 */, AMDGPU::S_CMP_LT_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18233 { 10327 /* s_decperflevel */, AMDGPU::S_DECPERFLEVEL, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18235 { 10356 /* s_endpgm */, AMDGPU::S_ENDPGM, Convert__EndpgmImm1_0, AMFBS_None, { MCK_EndpgmImm }, },
18270 { 10582 /* s_icache_inv */, AMDGPU::S_ICACHE_INV, Convert_NoOperands, AMFBS_None, { }, },
18271 { 10595 /* s_incperflevel */, AMDGPU::S_INCPERFLEVEL, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18392 { 11115 /* s_nop */, AMDGPU::S_NOP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18473 { 11617 /* s_sendmsg */, AMDGPU::S_SENDMSG, Convert__SendMsg1_0, AMFBS_None, { MCK_SendMsg }, },
18474 { 11627 /* s_sendmsghalt */, AMDGPU::S_SENDMSGHALT, Convert__SendMsg1_0, AMFBS_None, { MCK_SendMsg }, },
18479 { 11713 /* s_sethalt */, AMDGPU::S_SETHALT, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18480 { 11723 /* s_setkill */, AMDGPU::S_SETKILL, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18484 { 11745 /* s_setprio */, AMDGPU::S_SETPRIO, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18498 { 11827 /* s_sleep */, AMDGPU::S_SLEEP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18525 { 11969 /* s_trap */, AMDGPU::S_TRAP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18526 { 11976 /* s_ttracedata */, AMDGPU::S_TTRACEDATA, Convert_NoOperands, AMFBS_None, { }, },
18530 { 12028 /* s_waitcnt */, AMDGPU::S_WAITCNT, Convert__SWaitCnt1_0, AMFBS_None, { MCK_SWaitCnt }, },
21333 { 25672 /* v_readfirstlane_b32 */, AMDGPU::V_READFIRSTLANE_B32, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_SReg_32, MCK_VRegOrLds_32 }, },
70437 { 8774 /* s_branch */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70438 { 8774 /* s_branch */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70873 { 9567 /* s_cbranch_cdbgsys */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70874 { 9567 /* s_cbranch_cdbgsys */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70875 { 9585 /* s_cbranch_cdbgsys_and_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70876 { 9585 /* s_cbranch_cdbgsys_and_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70877 { 9612 /* s_cbranch_cdbgsys_or_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70878 { 9612 /* s_cbranch_cdbgsys_or_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70879 { 9638 /* s_cbranch_cdbguser */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70880 { 9638 /* s_cbranch_cdbguser */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70881 { 9657 /* s_cbranch_execnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70882 { 9657 /* s_cbranch_execnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70883 { 9674 /* s_cbranch_execz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70884 { 9674 /* s_cbranch_execz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70887 { 9739 /* s_cbranch_scc0 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70888 { 9739 /* s_cbranch_scc0 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70889 { 9754 /* s_cbranch_scc1 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70890 { 9754 /* s_cbranch_scc1 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70891 { 9769 /* s_cbranch_vccnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70892 { 9769 /* s_cbranch_vccnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70893 { 9785 /* s_cbranch_vccz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70894 { 9785 /* s_cbranch_vccz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70899 { 10356 /* s_endpgm */, 1 /* 0 */, MCK_EndpgmImm, AMFBS_None },
71053 { 11617 /* s_sendmsg */, 1 /* 0 */, MCK_SendMsg, AMFBS_None },
71054 { 11627 /* s_sendmsghalt */, 1 /* 0 */, MCK_SendMsg, AMFBS_None },
71095 { 12028 /* s_waitcnt */, 1 /* 0 */, MCK_SWaitCnt, AMFBS_None },