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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc22621 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22623 { 25297 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22625 { 25310 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22627 { 25323 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22629 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22631 { 25367 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22633 { 25384 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22635 { 25401 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22637 { 25414 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22639 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22641 { 25440 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22643 { 25453 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22645 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22647 { 25479 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22649 { 25492 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22651 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22653 { 25518 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22655 { 25534 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22657 { 25547 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
78947 { 25284 /* v_pk_add_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78948 { 25284 /* v_pk_add_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78949 { 25284 /* v_pk_add_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
78950 { 25284 /* v_pk_add_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
78951 { 25284 /* v_pk_add_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
78957 { 25297 /* v_pk_add_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78958 { 25297 /* v_pk_add_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78959 { 25297 /* v_pk_add_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
78960 { 25297 /* v_pk_add_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
78961 { 25297 /* v_pk_add_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
78967 { 25310 /* v_pk_add_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78968 { 25310 /* v_pk_add_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78969 { 25310 /* v_pk_add_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
78970 { 25310 /* v_pk_add_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
78971 { 25310 /* v_pk_add_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
78977 { 25323 /* v_pk_ashrrev_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78978 { 25323 /* v_pk_ashrrev_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78979 { 25323 /* v_pk_ashrrev_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
78980 { 25323 /* v_pk_ashrrev_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
78981 { 25323 /* v_pk_ashrrev_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
78987 { 25340 /* v_pk_fma_f16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78988 { 25340 /* v_pk_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78989 { 25340 /* v_pk_fma_f16 */, 32 /* 5 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
78990 { 25340 /* v_pk_fma_f16 */, 64 /* 6 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
78991 { 25340 /* v_pk_fma_f16 */, 128 /* 7 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
78997 { 25367 /* v_pk_lshlrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78998 { 25367 /* v_pk_lshlrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78999 { 25367 /* v_pk_lshlrev_b16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79000 { 25367 /* v_pk_lshlrev_b16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79001 { 25367 /* v_pk_lshlrev_b16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79007 { 25384 /* v_pk_lshrrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79008 { 25384 /* v_pk_lshrrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79009 { 25384 /* v_pk_lshrrev_b16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79010 { 25384 /* v_pk_lshrrev_b16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79011 { 25384 /* v_pk_lshrrev_b16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79017 { 25401 /* v_pk_mad_i16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79018 { 25401 /* v_pk_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79019 { 25401 /* v_pk_mad_i16 */, 32 /* 5 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79020 { 25401 /* v_pk_mad_i16 */, 64 /* 6 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79021 { 25401 /* v_pk_mad_i16 */, 128 /* 7 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79027 { 25414 /* v_pk_mad_u16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79028 { 25414 /* v_pk_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79029 { 25414 /* v_pk_mad_u16 */, 32 /* 5 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79030 { 25414 /* v_pk_mad_u16 */, 64 /* 6 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79031 { 25414 /* v_pk_mad_u16 */, 128 /* 7 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79037 { 25427 /* v_pk_max_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79038 { 25427 /* v_pk_max_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79039 { 25427 /* v_pk_max_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79040 { 25427 /* v_pk_max_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79041 { 25427 /* v_pk_max_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79047 { 25440 /* v_pk_max_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79048 { 25440 /* v_pk_max_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79049 { 25440 /* v_pk_max_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79050 { 25440 /* v_pk_max_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79051 { 25440 /* v_pk_max_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79057 { 25453 /* v_pk_max_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79058 { 25453 /* v_pk_max_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79059 { 25453 /* v_pk_max_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79060 { 25453 /* v_pk_max_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79061 { 25453 /* v_pk_max_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79067 { 25466 /* v_pk_min_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79068 { 25466 /* v_pk_min_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79069 { 25466 /* v_pk_min_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79070 { 25466 /* v_pk_min_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79071 { 25466 /* v_pk_min_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79077 { 25479 /* v_pk_min_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79078 { 25479 /* v_pk_min_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79079 { 25479 /* v_pk_min_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79080 { 25479 /* v_pk_min_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79081 { 25479 /* v_pk_min_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79087 { 25492 /* v_pk_min_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79088 { 25492 /* v_pk_min_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79089 { 25492 /* v_pk_min_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79090 { 25492 /* v_pk_min_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79091 { 25492 /* v_pk_min_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79097 { 25505 /* v_pk_mul_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79098 { 25505 /* v_pk_mul_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79099 { 25505 /* v_pk_mul_f16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79100 { 25505 /* v_pk_mul_f16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79101 { 25505 /* v_pk_mul_f16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79107 { 25518 /* v_pk_mul_lo_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79108 { 25518 /* v_pk_mul_lo_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79109 { 25518 /* v_pk_mul_lo_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79110 { 25518 /* v_pk_mul_lo_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79111 { 25518 /* v_pk_mul_lo_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79117 { 25534 /* v_pk_sub_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79118 { 25534 /* v_pk_sub_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79119 { 25534 /* v_pk_sub_i16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79120 { 25534 /* v_pk_sub_i16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79121 { 25534 /* v_pk_sub_i16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },
79127 { 25547 /* v_pk_sub_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79128 { 25547 /* v_pk_sub_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79129 { 25547 /* v_pk_sub_u16 */, 16 /* 4 */, MCK_ImmOpSelHi, AMFBS_HasVOP3PInsts },
79130 { 25547 /* v_pk_sub_u16 */, 32 /* 5 */, MCK_ImmNegLo, AMFBS_HasVOP3PInsts },
79131 { 25547 /* v_pk_sub_u16 */, 64 /* 6 */, MCK_ImmNegHi, AMFBS_HasVOP3PInsts },