reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
18449 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, }, 18451 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, }, 18453 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, }, 18455 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, }, 18457 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, }, 18459 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, }, 70993 { 11480 /* s_scratch_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 70994 { 11480 /* s_scratch_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 70997 { 11480 /* s_scratch_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 70998 { 11480 /* s_scratch_load_dword */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 70999 { 11480 /* s_scratch_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71003 { 11501 /* s_scratch_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71004 { 11501 /* s_scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71007 { 11501 /* s_scratch_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71008 { 11501 /* s_scratch_load_dwordx2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71009 { 11501 /* s_scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71013 { 11524 /* s_scratch_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71014 { 11524 /* s_scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71017 { 11524 /* s_scratch_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71018 { 11524 /* s_scratch_load_dwordx4 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus }, 71019 { 11524 /* s_scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },