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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc17602 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17604 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17606 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17608 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17610 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17612 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17614 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17616 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17618 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17620 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17622 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17624 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17626 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17628 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17630 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17632 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17634 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17636 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17638 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17640 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17642 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17644 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17646 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17648 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17650 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17652 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17654 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17656 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17658 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17660 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17662 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17664 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17666 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17668 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17670 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17672 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17674 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17676 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17678 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17680 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17682 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17684 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17686 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17688 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17690 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17692 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17694 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17696 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17698 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17700 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17702 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17704 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17706 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17708 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17710 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17712 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17714 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17716 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17718 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17720 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17722 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17724 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17726 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17728 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17730 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17732 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17734 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17736 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17738 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17740 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17742 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17744 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17746 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17748 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17750 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17752 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17754 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17756 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17758 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17760 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17762 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17764 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17766 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17768 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17770 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17772 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17774 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17776 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17778 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17780 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17782 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17784 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17786 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17788 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17790 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17792 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17794 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17796 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17798 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17800 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17802 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17804 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17806 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17808 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17867 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17869 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17871 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17873 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17875 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17877 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17879 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17881 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17883 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17885 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17887 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17889 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17891 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17893 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17895 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17897 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17899 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17901 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17903 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17905 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17907 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17909 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17911 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17913 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17915 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17917 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17919 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17921 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17923 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17925 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17927 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17929 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17931 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17933 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17935 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17937 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17939 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17941 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17943 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17945 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17947 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17949 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17951 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17953 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17955 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17957 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17959 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17961 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17963 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17965 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17967 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17969 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17971 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17973 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17975 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17977 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17979 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17981 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17983 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17985 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17987 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17989 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17991 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17993 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17995 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17997 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17999 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18001 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18003 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18005 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18007 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18009 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18011 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18013 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18015 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18017 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18019 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18021 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18023 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18025 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18027 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18029 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18031 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18033 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18035 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18037 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18039 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18041 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18043 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18045 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18047 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18049 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18051 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18053 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18055 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18057 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18059 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18061 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18063 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18065 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18067 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18069 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18071 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18073 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18217 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_SGPR_gfx10, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_SReg_32 }, },
18219 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_IMM_gfx10, Convert__Reg1_0__ImmSMRDOffset201_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
18221 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_SReg_32 }, },
18223 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_IMM_gfx10, Convert__Reg1_0__ImmSMRDOffset201_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
70125 { 8112 /* s_atomic_add */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70127 { 8112 /* s_atomic_add */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70128 { 8112 /* s_atomic_add */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70131 { 8112 /* s_atomic_add */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70133 { 8112 /* s_atomic_add */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70134 { 8112 /* s_atomic_add */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70137 { 8125 /* s_atomic_add_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70139 { 8125 /* s_atomic_add_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70140 { 8125 /* s_atomic_add_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70143 { 8125 /* s_atomic_add_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70145 { 8125 /* s_atomic_add_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70146 { 8125 /* s_atomic_add_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70149 { 8141 /* s_atomic_and */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70151 { 8141 /* s_atomic_and */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70152 { 8141 /* s_atomic_and */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70155 { 8141 /* s_atomic_and */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70157 { 8141 /* s_atomic_and */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70158 { 8141 /* s_atomic_and */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70161 { 8154 /* s_atomic_and_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70163 { 8154 /* s_atomic_and_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70164 { 8154 /* s_atomic_and_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70167 { 8154 /* s_atomic_and_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70169 { 8154 /* s_atomic_and_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70170 { 8154 /* s_atomic_and_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70173 { 8170 /* s_atomic_cmpswap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70175 { 8170 /* s_atomic_cmpswap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70176 { 8170 /* s_atomic_cmpswap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70179 { 8170 /* s_atomic_cmpswap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70181 { 8170 /* s_atomic_cmpswap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70182 { 8170 /* s_atomic_cmpswap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70185 { 8187 /* s_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70187 { 8187 /* s_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70188 { 8187 /* s_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70191 { 8187 /* s_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70193 { 8187 /* s_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70194 { 8187 /* s_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70197 { 8207 /* s_atomic_dec */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70199 { 8207 /* s_atomic_dec */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70200 { 8207 /* s_atomic_dec */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70203 { 8207 /* s_atomic_dec */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70205 { 8207 /* s_atomic_dec */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70206 { 8207 /* s_atomic_dec */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70209 { 8220 /* s_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70211 { 8220 /* s_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70212 { 8220 /* s_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70215 { 8220 /* s_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70217 { 8220 /* s_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70218 { 8220 /* s_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70221 { 8236 /* s_atomic_inc */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70223 { 8236 /* s_atomic_inc */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70224 { 8236 /* s_atomic_inc */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70227 { 8236 /* s_atomic_inc */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70229 { 8236 /* s_atomic_inc */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70230 { 8236 /* s_atomic_inc */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70233 { 8249 /* s_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70235 { 8249 /* s_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70236 { 8249 /* s_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70239 { 8249 /* s_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70241 { 8249 /* s_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70242 { 8249 /* s_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70245 { 8265 /* s_atomic_or */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70247 { 8265 /* s_atomic_or */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70248 { 8265 /* s_atomic_or */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70251 { 8265 /* s_atomic_or */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70253 { 8265 /* s_atomic_or */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70254 { 8265 /* s_atomic_or */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70257 { 8277 /* s_atomic_or_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70259 { 8277 /* s_atomic_or_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70260 { 8277 /* s_atomic_or_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70263 { 8277 /* s_atomic_or_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70265 { 8277 /* s_atomic_or_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70266 { 8277 /* s_atomic_or_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70269 { 8292 /* s_atomic_smax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70271 { 8292 /* s_atomic_smax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70272 { 8292 /* s_atomic_smax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70275 { 8292 /* s_atomic_smax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70277 { 8292 /* s_atomic_smax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70278 { 8292 /* s_atomic_smax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70281 { 8306 /* s_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70283 { 8306 /* s_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70284 { 8306 /* s_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70287 { 8306 /* s_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70289 { 8306 /* s_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70290 { 8306 /* s_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70293 { 8323 /* s_atomic_smin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70295 { 8323 /* s_atomic_smin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70296 { 8323 /* s_atomic_smin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70299 { 8323 /* s_atomic_smin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70301 { 8323 /* s_atomic_smin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70302 { 8323 /* s_atomic_smin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70305 { 8337 /* s_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70307 { 8337 /* s_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70308 { 8337 /* s_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70311 { 8337 /* s_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70313 { 8337 /* s_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70314 { 8337 /* s_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70317 { 8354 /* s_atomic_sub */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70319 { 8354 /* s_atomic_sub */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70320 { 8354 /* s_atomic_sub */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70323 { 8354 /* s_atomic_sub */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70325 { 8354 /* s_atomic_sub */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70326 { 8354 /* s_atomic_sub */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70329 { 8367 /* s_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70331 { 8367 /* s_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70332 { 8367 /* s_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70335 { 8367 /* s_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70337 { 8367 /* s_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70338 { 8367 /* s_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70341 { 8383 /* s_atomic_swap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70343 { 8383 /* s_atomic_swap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70344 { 8383 /* s_atomic_swap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70347 { 8383 /* s_atomic_swap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70349 { 8383 /* s_atomic_swap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70350 { 8383 /* s_atomic_swap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70353 { 8397 /* s_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70355 { 8397 /* s_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70356 { 8397 /* s_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70359 { 8397 /* s_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70361 { 8397 /* s_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70362 { 8397 /* s_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70365 { 8414 /* s_atomic_umax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70367 { 8414 /* s_atomic_umax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70368 { 8414 /* s_atomic_umax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70371 { 8414 /* s_atomic_umax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70373 { 8414 /* s_atomic_umax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70374 { 8414 /* s_atomic_umax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70377 { 8428 /* s_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70379 { 8428 /* s_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70380 { 8428 /* s_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70383 { 8428 /* s_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70385 { 8428 /* s_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70386 { 8428 /* s_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70389 { 8445 /* s_atomic_umin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70391 { 8445 /* s_atomic_umin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70392 { 8445 /* s_atomic_umin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70395 { 8445 /* s_atomic_umin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70397 { 8445 /* s_atomic_umin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70398 { 8445 /* s_atomic_umin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70401 { 8459 /* s_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70403 { 8459 /* s_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70404 { 8459 /* s_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70407 { 8459 /* s_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70409 { 8459 /* s_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70410 { 8459 /* s_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70413 { 8476 /* s_atomic_xor */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70415 { 8476 /* s_atomic_xor */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70416 { 8476 /* s_atomic_xor */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70419 { 8476 /* s_atomic_xor */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70421 { 8476 /* s_atomic_xor */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70422 { 8476 /* s_atomic_xor */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70425 { 8489 /* s_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70427 { 8489 /* s_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70428 { 8489 /* s_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70431 { 8489 /* s_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70433 { 8489 /* s_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70434 { 8489 /* s_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70439 { 8805 /* s_buffer_atomic_add */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70441 { 8805 /* s_buffer_atomic_add */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70442 { 8805 /* s_buffer_atomic_add */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70445 { 8805 /* s_buffer_atomic_add */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70447 { 8805 /* s_buffer_atomic_add */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70448 { 8805 /* s_buffer_atomic_add */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70451 { 8825 /* s_buffer_atomic_add_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70453 { 8825 /* s_buffer_atomic_add_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70454 { 8825 /* s_buffer_atomic_add_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70457 { 8825 /* s_buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70459 { 8825 /* s_buffer_atomic_add_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70460 { 8825 /* s_buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70463 { 8848 /* s_buffer_atomic_and */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70465 { 8848 /* s_buffer_atomic_and */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70466 { 8848 /* s_buffer_atomic_and */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70469 { 8848 /* s_buffer_atomic_and */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70471 { 8848 /* s_buffer_atomic_and */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70472 { 8848 /* s_buffer_atomic_and */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70475 { 8868 /* s_buffer_atomic_and_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70477 { 8868 /* s_buffer_atomic_and_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70478 { 8868 /* s_buffer_atomic_and_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70481 { 8868 /* s_buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70483 { 8868 /* s_buffer_atomic_and_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70484 { 8868 /* s_buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70487 { 8891 /* s_buffer_atomic_cmpswap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70489 { 8891 /* s_buffer_atomic_cmpswap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70490 { 8891 /* s_buffer_atomic_cmpswap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70493 { 8891 /* s_buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70495 { 8891 /* s_buffer_atomic_cmpswap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70496 { 8891 /* s_buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70499 { 8915 /* s_buffer_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70501 { 8915 /* s_buffer_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70502 { 8915 /* s_buffer_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70505 { 8915 /* s_buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70507 { 8915 /* s_buffer_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70508 { 8915 /* s_buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70511 { 8942 /* s_buffer_atomic_dec */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70513 { 8942 /* s_buffer_atomic_dec */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70514 { 8942 /* s_buffer_atomic_dec */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70517 { 8942 /* s_buffer_atomic_dec */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70519 { 8942 /* s_buffer_atomic_dec */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70520 { 8942 /* s_buffer_atomic_dec */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70523 { 8962 /* s_buffer_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70525 { 8962 /* s_buffer_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70526 { 8962 /* s_buffer_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70529 { 8962 /* s_buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70531 { 8962 /* s_buffer_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70532 { 8962 /* s_buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70535 { 8985 /* s_buffer_atomic_inc */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70537 { 8985 /* s_buffer_atomic_inc */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70538 { 8985 /* s_buffer_atomic_inc */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70541 { 8985 /* s_buffer_atomic_inc */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70543 { 8985 /* s_buffer_atomic_inc */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70544 { 8985 /* s_buffer_atomic_inc */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70547 { 9005 /* s_buffer_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70549 { 9005 /* s_buffer_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70550 { 9005 /* s_buffer_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70553 { 9005 /* s_buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70555 { 9005 /* s_buffer_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70556 { 9005 /* s_buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70559 { 9028 /* s_buffer_atomic_or */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70561 { 9028 /* s_buffer_atomic_or */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70562 { 9028 /* s_buffer_atomic_or */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70565 { 9028 /* s_buffer_atomic_or */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70567 { 9028 /* s_buffer_atomic_or */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70568 { 9028 /* s_buffer_atomic_or */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70571 { 9047 /* s_buffer_atomic_or_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70573 { 9047 /* s_buffer_atomic_or_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70574 { 9047 /* s_buffer_atomic_or_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70577 { 9047 /* s_buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70579 { 9047 /* s_buffer_atomic_or_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70580 { 9047 /* s_buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70583 { 9069 /* s_buffer_atomic_smax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70585 { 9069 /* s_buffer_atomic_smax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70586 { 9069 /* s_buffer_atomic_smax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70589 { 9069 /* s_buffer_atomic_smax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70591 { 9069 /* s_buffer_atomic_smax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70592 { 9069 /* s_buffer_atomic_smax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70595 { 9090 /* s_buffer_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70597 { 9090 /* s_buffer_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70598 { 9090 /* s_buffer_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70601 { 9090 /* s_buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70603 { 9090 /* s_buffer_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70604 { 9090 /* s_buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70607 { 9114 /* s_buffer_atomic_smin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70609 { 9114 /* s_buffer_atomic_smin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70610 { 9114 /* s_buffer_atomic_smin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70613 { 9114 /* s_buffer_atomic_smin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70615 { 9114 /* s_buffer_atomic_smin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70616 { 9114 /* s_buffer_atomic_smin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70619 { 9135 /* s_buffer_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70621 { 9135 /* s_buffer_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70622 { 9135 /* s_buffer_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70625 { 9135 /* s_buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70627 { 9135 /* s_buffer_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70628 { 9135 /* s_buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70631 { 9159 /* s_buffer_atomic_sub */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70633 { 9159 /* s_buffer_atomic_sub */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70634 { 9159 /* s_buffer_atomic_sub */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70637 { 9159 /* s_buffer_atomic_sub */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70639 { 9159 /* s_buffer_atomic_sub */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70640 { 9159 /* s_buffer_atomic_sub */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70643 { 9179 /* s_buffer_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70645 { 9179 /* s_buffer_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70646 { 9179 /* s_buffer_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70649 { 9179 /* s_buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70651 { 9179 /* s_buffer_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70652 { 9179 /* s_buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70655 { 9202 /* s_buffer_atomic_swap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70657 { 9202 /* s_buffer_atomic_swap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70658 { 9202 /* s_buffer_atomic_swap */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70661 { 9202 /* s_buffer_atomic_swap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70663 { 9202 /* s_buffer_atomic_swap */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70664 { 9202 /* s_buffer_atomic_swap */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70667 { 9223 /* s_buffer_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70669 { 9223 /* s_buffer_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70670 { 9223 /* s_buffer_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70673 { 9223 /* s_buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70675 { 9223 /* s_buffer_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70676 { 9223 /* s_buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70679 { 9247 /* s_buffer_atomic_umax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70681 { 9247 /* s_buffer_atomic_umax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70682 { 9247 /* s_buffer_atomic_umax */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70685 { 9247 /* s_buffer_atomic_umax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70687 { 9247 /* s_buffer_atomic_umax */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70688 { 9247 /* s_buffer_atomic_umax */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70691 { 9268 /* s_buffer_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70693 { 9268 /* s_buffer_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70694 { 9268 /* s_buffer_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70697 { 9268 /* s_buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70699 { 9268 /* s_buffer_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70700 { 9268 /* s_buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70703 { 9292 /* s_buffer_atomic_umin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70705 { 9292 /* s_buffer_atomic_umin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70706 { 9292 /* s_buffer_atomic_umin */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70709 { 9292 /* s_buffer_atomic_umin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70711 { 9292 /* s_buffer_atomic_umin */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70712 { 9292 /* s_buffer_atomic_umin */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70715 { 9313 /* s_buffer_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70717 { 9313 /* s_buffer_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70718 { 9313 /* s_buffer_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70721 { 9313 /* s_buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70723 { 9313 /* s_buffer_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70724 { 9313 /* s_buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70727 { 9337 /* s_buffer_atomic_xor */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70729 { 9337 /* s_buffer_atomic_xor */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70730 { 9337 /* s_buffer_atomic_xor */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70733 { 9337 /* s_buffer_atomic_xor */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70735 { 9337 /* s_buffer_atomic_xor */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70736 { 9337 /* s_buffer_atomic_xor */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70739 { 9357 /* s_buffer_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70741 { 9357 /* s_buffer_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70742 { 9357 /* s_buffer_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70745 { 9357 /* s_buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70747 { 9357 /* s_buffer_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70748 { 9357 /* s_buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmDLC, AMFBS_HasScalarAtomics_isGFX10Plus },
70895 { 10232 /* s_dcache_discard */, 2 /* 1 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },
70897 { 10249 /* s_dcache_discard_x2 */, 2 /* 1 */, MCK_ImmSMRDOffset20, AMFBS_HasScalarAtomics_isGFX10Plus },