reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
22800 { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 22803 { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23039 { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23042 { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23045 { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23053 { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 73046 { 13378 /* v_add_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73047 { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73048 { 13378 /* v_add_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73049 { 13378 /* v_add_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73050 { 13378 /* v_add_u32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73051 { 13378 /* v_add_u32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73072 { 13402 /* v_addc_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73073 { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73074 { 13402 /* v_addc_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73075 { 13402 /* v_addc_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73076 { 13402 /* v_addc_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 73077 { 13402 /* v_addc_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79839 { 26090 /* v_sub_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79840 { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79841 { 26090 /* v_sub_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79842 { 26090 /* v_sub_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79843 { 26090 /* v_sub_u32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79844 { 26090 /* v_sub_u32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79865 { 26114 /* v_subb_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79866 { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79867 { 26114 /* v_subb_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79868 { 26114 /* v_subb_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79869 { 26114 /* v_subb_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79870 { 26114 /* v_subb_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79891 { 26142 /* v_subbrev_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79892 { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79893 { 26142 /* v_subbrev_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79894 { 26142 /* v_subbrev_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79895 { 26142 /* v_subbrev_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 79896 { 26142 /* v_subbrev_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 80082 { 26259 /* v_subrev_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 80083 { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 80084 { 26259 /* v_subrev_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 80085 { 26259 /* v_subrev_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 80086 { 26259 /* v_subrev_u32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only }, 80087 { 26259 /* v_subrev_u32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA_isGFX8Only },