reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

22798   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22804   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22806   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22807   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22809   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22811   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22813   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22815   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22817   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22819   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22821   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22823   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22825   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22827   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22829   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22831   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22833   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22835   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22837   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22839   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22841   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22843   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22845   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22847   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22849   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22851   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22853   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22855   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22857   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22859   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22861   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22863   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22865   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22867   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22869   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22871   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22873   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22875   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22877   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22879   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22881   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22883   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22885   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22887   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22889   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22891   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22893   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22895   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22897   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22899   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22901   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22903   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22905   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22907   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22909   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22911   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22913   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22915   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22917   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22919   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22921   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22923   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22925   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22927   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22929   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22931   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22933   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22935   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22937   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22939   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22941   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22948   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22950   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22951   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22954   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22955   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22956   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22957   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22958   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22959   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22960   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22961   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22963   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22966   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22967   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22969   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22971   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22973   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22974   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22975   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22977   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22980   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22982   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22984   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22987   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22990   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22992   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22994   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22996   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22998   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23000   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23002   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23004   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23006   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23007   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23008   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23010   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23011   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23012   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23013   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23014   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23016   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23017   { 25176 /* v_nop */, AMDGPU::V_NOP_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, {  }, },
23018   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23019   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23021   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23022   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23024   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23026   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23029   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23031   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23037   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23051   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23055   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23057   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72958   { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
72959   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
72960   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
72961   { 13261 /* v_add_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
72962   { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
72963   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
73089   { 13444 /* v_and_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73090   { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73091   { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73092   { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73093   { 13444 /* v_and_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73094   { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
73134   { 13503 /* v_ashrrev_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73135   { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73136   { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73137   { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73138   { 13503 /* v_ashrrev_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73139   { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
73158   { 13586 /* v_bfrev_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73159   { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73160   { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73161   { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73162   { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
73225   { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73226   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73227   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73228   { 13609 /* v_ceil_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73229   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
73297   { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73298   { 13677 /* v_cmp_class_f32 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73299   { 13677 /* v_cmp_class_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73300   { 13677 /* v_cmp_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73301   { 13677 /* v_cmp_class_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73343   { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73344   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73345   { 13779 /* v_cmp_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73346   { 13779 /* v_cmp_eq_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73381   { 13869 /* v_cmp_eq_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73382   { 13869 /* v_cmp_eq_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73383   { 13869 /* v_cmp_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73384   { 13869 /* v_cmp_eq_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73413   { 13959 /* v_cmp_eq_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73414   { 13959 /* v_cmp_eq_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73415   { 13959 /* v_cmp_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73416   { 13959 /* v_cmp_eq_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73455   { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73456   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73457   { 14047 /* v_cmp_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73458   { 14047 /* v_cmp_f_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73488   { 14131 /* v_cmp_f_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73489   { 14131 /* v_cmp_f_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73490   { 14131 /* v_cmp_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73491   { 14131 /* v_cmp_f_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73515   { 14215 /* v_cmp_f_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73516   { 14215 /* v_cmp_f_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73517   { 14215 /* v_cmp_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73518   { 14215 /* v_cmp_f_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73557   { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73558   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73559   { 14301 /* v_cmp_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73560   { 14301 /* v_cmp_ge_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73595   { 14391 /* v_cmp_ge_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73596   { 14391 /* v_cmp_ge_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73597   { 14391 /* v_cmp_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73598   { 14391 /* v_cmp_ge_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73627   { 14481 /* v_cmp_ge_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73628   { 14481 /* v_cmp_ge_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73629   { 14481 /* v_cmp_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73630   { 14481 /* v_cmp_ge_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73669   { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73670   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73671   { 14571 /* v_cmp_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73672   { 14571 /* v_cmp_gt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73707   { 14661 /* v_cmp_gt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73708   { 14661 /* v_cmp_gt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73709   { 14661 /* v_cmp_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73710   { 14661 /* v_cmp_gt_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73739   { 14751 /* v_cmp_gt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73740   { 14751 /* v_cmp_gt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73741   { 14751 /* v_cmp_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73742   { 14751 /* v_cmp_gt_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73781   { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73782   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73783   { 14841 /* v_cmp_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73784   { 14841 /* v_cmp_le_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73819   { 14931 /* v_cmp_le_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73820   { 14931 /* v_cmp_le_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73821   { 14931 /* v_cmp_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73822   { 14931 /* v_cmp_le_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73851   { 15021 /* v_cmp_le_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73852   { 15021 /* v_cmp_le_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73853   { 15021 /* v_cmp_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73854   { 15021 /* v_cmp_le_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73893   { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73894   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73895   { 15111 /* v_cmp_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73896   { 15111 /* v_cmp_lg_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73941   { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73942   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73943   { 15201 /* v_cmp_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73944   { 15201 /* v_cmp_lt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
73979   { 15291 /* v_cmp_lt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
73980   { 15291 /* v_cmp_lt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73981   { 15291 /* v_cmp_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73982   { 15291 /* v_cmp_lt_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74011   { 15381 /* v_cmp_lt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74012   { 15381 /* v_cmp_lt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74013   { 15381 /* v_cmp_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74014   { 15381 /* v_cmp_lt_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74043   { 15471 /* v_cmp_ne_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74044   { 15471 /* v_cmp_ne_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74045   { 15471 /* v_cmp_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74046   { 15471 /* v_cmp_ne_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74075   { 15561 /* v_cmp_ne_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74076   { 15561 /* v_cmp_ne_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74077   { 15561 /* v_cmp_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74078   { 15561 /* v_cmp_ne_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74117   { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74118   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74119   { 15653 /* v_cmp_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74120   { 15653 /* v_cmp_neq_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74165   { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74166   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74167   { 15749 /* v_cmp_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74168   { 15749 /* v_cmp_nge_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74213   { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74214   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74215   { 15845 /* v_cmp_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74216   { 15845 /* v_cmp_ngt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74261   { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74262   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74263   { 15941 /* v_cmp_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74264   { 15941 /* v_cmp_nle_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74309   { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74310   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74311   { 16037 /* v_cmp_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74312   { 16037 /* v_cmp_nlg_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74357   { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74358   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74359   { 16133 /* v_cmp_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74360   { 16133 /* v_cmp_nlt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74405   { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74406   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74407   { 16225 /* v_cmp_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74408   { 16225 /* v_cmp_o_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74438   { 16309 /* v_cmp_t_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74439   { 16309 /* v_cmp_t_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74440   { 16309 /* v_cmp_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74441   { 16309 /* v_cmp_t_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74465   { 16393 /* v_cmp_t_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74466   { 16393 /* v_cmp_t_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74467   { 16393 /* v_cmp_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74468   { 16393 /* v_cmp_t_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74507   { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74508   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74509   { 16481 /* v_cmp_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74510   { 16481 /* v_cmp_tru_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74555   { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74556   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74557   { 16573 /* v_cmp_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74558   { 16573 /* v_cmp_u_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74791   { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74792   { 18811 /* v_cmpx_class_f32 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74793   { 18811 /* v_cmpx_class_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74794   { 18811 /* v_cmpx_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74795   { 18811 /* v_cmpx_class_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74832   { 18919 /* v_cmpx_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74833   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74834   { 18919 /* v_cmpx_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74835   { 18919 /* v_cmpx_eq_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74865   { 19015 /* v_cmpx_eq_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74866   { 19015 /* v_cmpx_eq_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74867   { 19015 /* v_cmpx_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74868   { 19015 /* v_cmpx_eq_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74892   { 19111 /* v_cmpx_eq_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74893   { 19111 /* v_cmpx_eq_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74894   { 19111 /* v_cmpx_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74895   { 19111 /* v_cmpx_eq_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74929   { 19205 /* v_cmpx_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74930   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74931   { 19205 /* v_cmpx_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74932   { 19205 /* v_cmpx_f_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74959   { 19295 /* v_cmpx_f_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74960   { 19295 /* v_cmpx_f_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74961   { 19295 /* v_cmpx_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74962   { 19295 /* v_cmpx_f_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
74983   { 19385 /* v_cmpx_f_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
74984   { 19385 /* v_cmpx_f_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74985   { 19385 /* v_cmpx_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74986   { 19385 /* v_cmpx_f_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75020   { 19477 /* v_cmpx_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75021   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75022   { 19477 /* v_cmpx_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75023   { 19477 /* v_cmpx_ge_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75053   { 19573 /* v_cmpx_ge_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75054   { 19573 /* v_cmpx_ge_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75055   { 19573 /* v_cmpx_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75056   { 19573 /* v_cmpx_ge_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75080   { 19669 /* v_cmpx_ge_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75081   { 19669 /* v_cmpx_ge_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75082   { 19669 /* v_cmpx_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75083   { 19669 /* v_cmpx_ge_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75117   { 19765 /* v_cmpx_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75118   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75119   { 19765 /* v_cmpx_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75120   { 19765 /* v_cmpx_gt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75150   { 19861 /* v_cmpx_gt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75151   { 19861 /* v_cmpx_gt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75152   { 19861 /* v_cmpx_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75153   { 19861 /* v_cmpx_gt_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75177   { 19957 /* v_cmpx_gt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75178   { 19957 /* v_cmpx_gt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75179   { 19957 /* v_cmpx_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75180   { 19957 /* v_cmpx_gt_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75214   { 20053 /* v_cmpx_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75215   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75216   { 20053 /* v_cmpx_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75217   { 20053 /* v_cmpx_le_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75247   { 20149 /* v_cmpx_le_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75248   { 20149 /* v_cmpx_le_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75249   { 20149 /* v_cmpx_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75250   { 20149 /* v_cmpx_le_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75274   { 20245 /* v_cmpx_le_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75275   { 20245 /* v_cmpx_le_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75276   { 20245 /* v_cmpx_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75277   { 20245 /* v_cmpx_le_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75311   { 20341 /* v_cmpx_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75312   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75313   { 20341 /* v_cmpx_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75314   { 20341 /* v_cmpx_lg_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75354   { 20437 /* v_cmpx_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75355   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75356   { 20437 /* v_cmpx_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75357   { 20437 /* v_cmpx_lt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75387   { 20533 /* v_cmpx_lt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75388   { 20533 /* v_cmpx_lt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75389   { 20533 /* v_cmpx_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75390   { 20533 /* v_cmpx_lt_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75414   { 20629 /* v_cmpx_lt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75415   { 20629 /* v_cmpx_lt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75416   { 20629 /* v_cmpx_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75417   { 20629 /* v_cmpx_lt_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75441   { 20725 /* v_cmpx_ne_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75442   { 20725 /* v_cmpx_ne_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75443   { 20725 /* v_cmpx_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75444   { 20725 /* v_cmpx_ne_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75468   { 20821 /* v_cmpx_ne_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75469   { 20821 /* v_cmpx_ne_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75470   { 20821 /* v_cmpx_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75471   { 20821 /* v_cmpx_ne_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75505   { 20919 /* v_cmpx_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75506   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75507   { 20919 /* v_cmpx_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75508   { 20919 /* v_cmpx_neq_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75548   { 21021 /* v_cmpx_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75549   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75550   { 21021 /* v_cmpx_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75551   { 21021 /* v_cmpx_nge_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75591   { 21123 /* v_cmpx_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75592   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75593   { 21123 /* v_cmpx_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75594   { 21123 /* v_cmpx_ngt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75634   { 21225 /* v_cmpx_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75635   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75636   { 21225 /* v_cmpx_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75637   { 21225 /* v_cmpx_nle_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75677   { 21327 /* v_cmpx_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75678   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75679   { 21327 /* v_cmpx_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75680   { 21327 /* v_cmpx_nlg_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75720   { 21429 /* v_cmpx_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75721   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75722   { 21429 /* v_cmpx_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75723   { 21429 /* v_cmpx_nlt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75763   { 21527 /* v_cmpx_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75764   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75765   { 21527 /* v_cmpx_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75766   { 21527 /* v_cmpx_o_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75793   { 21617 /* v_cmpx_t_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75794   { 21617 /* v_cmpx_t_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75795   { 21617 /* v_cmpx_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75796   { 21617 /* v_cmpx_t_i32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75817   { 21707 /* v_cmpx_t_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75818   { 21707 /* v_cmpx_t_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75819   { 21707 /* v_cmpx_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75820   { 21707 /* v_cmpx_t_u32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75854   { 21801 /* v_cmpx_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75855   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75856   { 21801 /* v_cmpx_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75857   { 21801 /* v_cmpx_tru_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75897   { 21899 /* v_cmpx_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75898   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75899   { 21899 /* v_cmpx_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75900   { 21899 /* v_cmpx_u_f32 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75952   { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
75953   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75954   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
75955   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75956   { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
75957   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76017   { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76018   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76019   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76020   { 21983 /* v_cos_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76021   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76092   { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76093   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76094   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76095   { 22045 /* v_cvt_f16_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76096   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76195   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA_HasSDWA },
76196   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76197   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76198   { 22087 /* v_cvt_f32_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76199   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76244   { 22115 /* v_cvt_f32_i32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76245   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76246   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76247   { 22115 /* v_cvt_f32_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76248   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76278   { 22129 /* v_cvt_f32_u32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76279   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76280   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76281   { 22129 /* v_cvt_f32_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76282   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76312   { 22143 /* v_cvt_f32_ubyte0 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76313   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76314   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76315   { 22143 /* v_cvt_f32_ubyte0 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76316   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76346   { 22160 /* v_cvt_f32_ubyte1 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76347   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76348   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76349   { 22160 /* v_cvt_f32_ubyte1 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76350   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76380   { 22177 /* v_cvt_f32_ubyte2 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76381   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76382   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76383   { 22177 /* v_cvt_f32_ubyte2 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76384   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76414   { 22194 /* v_cvt_f32_ubyte3 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76415   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76416   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76417   { 22194 /* v_cvt_f32_ubyte3 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76418   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76465   { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76466   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76467   { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76468   { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76469   { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76531   { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76532   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76533   { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76534   { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76535   { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76639   { 22351 /* v_cvt_off_f32_i4 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
76640   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76641   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76642   { 22351 /* v_cvt_off_f32_i4 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76643   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76717   { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76718   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76719   { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76720   { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76721   { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
76783   { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76784   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76785   { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76786   { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76787   { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77022   { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77023   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77024   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77025   { 22909 /* v_exp_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77026   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77078   { 22936 /* v_ffbh_i32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
77079   { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77080   { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77081   { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77082   { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77104   { 22947 /* v_ffbh_u32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
77105   { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77106   { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77107   { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77108   { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77130   { 22958 /* v_ffbl_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
77131   { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77132   { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77133   { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77134   { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77197   { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77198   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77199   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77200   { 22981 /* v_floor_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77201   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77375   { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77376   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77377   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77378   { 23180 /* v_fract_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77379   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77452   { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77453   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77454   { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77455   { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77456   { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77531   { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77532   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77533   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77534   { 23281 /* v_frexp_mant_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77535   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77765   { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77766   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77767   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77768   { 23511 /* v_log_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77769   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77842   { 23603 /* v_lshlrev_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
77843   { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77844   { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77845   { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77846   { 23603 /* v_lshlrev_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
77847   { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77887   { 23667 /* v_lshrrev_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
77888   { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77889   { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77890   { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77891   { 23667 /* v_lshrrev_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
77892   { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
77935   { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77936   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77937   { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77938   { 23705 /* v_mac_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77939   { 23705 /* v_mac_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
77940   { 23705 /* v_mac_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78131   { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78132   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78133   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78134   { 24094 /* v_max_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78135   { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78136   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78193   { 24124 /* v_max_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78194   { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78195   { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78196   { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78197   { 24124 /* v_max_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78198   { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78241   { 24161 /* v_max_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78242   { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78243   { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78244   { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78245   { 24161 /* v_max_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78246   { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78420   { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78421   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78422   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78423   { 24785 /* v_min_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78424   { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78425   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78482   { 24815 /* v_min_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78483   { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78484   { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78485   { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78486   { 24815 /* v_min_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78487   { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78530   { 24852 /* v_min_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78531   { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78532   { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78533   { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78534   { 24852 /* v_min_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78535   { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78554   { 24862 /* v_mov_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78555   { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78556   { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78557   { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78558   { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78580   { 24872 /* v_mov_fed_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78581   { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78582   { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78583   { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78584   { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78664   { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78665   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78666   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78667   { 24999 /* v_mul_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78668   { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78669   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78710   { 25032 /* v_mul_hi_i32_i24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78711   { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78712   { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78713   { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78714   { 25032 /* v_mul_hi_i32_i24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78715   { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78739   { 25062 /* v_mul_hi_u32_u24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78740   { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78741   { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78742   { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78743   { 25062 /* v_mul_hi_u32_u24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78744   { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78768   { 25079 /* v_mul_i32_i24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78769   { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78770   { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78771   { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78772   { 25079 /* v_mul_i32_i24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78773   { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78802   { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78803   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78804   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78805   { 25093 /* v_mul_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78806   { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78807   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78855   { 25149 /* v_mul_u32_u24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78856   { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78857   { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78858   { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78859   { 25149 /* v_mul_u32_u24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78860   { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78885   { 25182 /* v_not_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78886   { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78887   { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78888   { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78889   { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
78916   { 25202 /* v_or_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
78917   { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78918   { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78919   { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78920   { 25202 /* v_or_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
78921   { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79188   { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79189   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79190   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79191   { 25619 /* v_rcp_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79192   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79236   { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79237   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79238   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79239   { 25639 /* v_rcp_iflag_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79240   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79314   { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79315   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79316   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79317   { 25719 /* v_rndne_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79318   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79404   { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79405   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79406   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79407   { 25785 /* v_rsq_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79408   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79538   { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79539   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79540   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79541   { 25916 /* v_sin_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79542   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79613   { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79614   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79615   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79616   { 25937 /* v_sqrt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79617   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
79760   { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79761   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79762   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79763   { 25998 /* v_sub_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79764   { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
79765   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
80007   { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
80008   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
80009   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
80010   { 26204 /* v_subrev_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
80011   { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
80012   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
80147   { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
80148   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
80149   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
80150   { 26326 /* v_trunc_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
80151   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },
80224   { 26398 /* v_xor_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA_HasSDWA },
80225   { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
80226   { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
80227   { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
80228   { 26398 /* v_xor_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA_HasSDWA },
80229   { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA_HasSDWA },