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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc23068 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23075 { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23078 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23517 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23524 { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23527 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23530 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23538 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23545 { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72897 { 13238 /* v_add_co_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72898 { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72899 { 13238 /* v_add_co_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72900 { 13238 /* v_add_co_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72901 { 13238 /* v_add_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72902 { 13238 /* v_add_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73040 { 13378 /* v_add_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73041 { 13378 /* v_add_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73042 { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73043 { 13378 /* v_add_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73044 { 13378 /* v_add_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73045 { 13378 /* v_add_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73058 { 13388 /* v_addc_co_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73059 { 13388 /* v_addc_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73060 { 13388 /* v_addc_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73061 { 13388 /* v_addc_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73062 { 13388 /* v_addc_co_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73063 { 13388 /* v_addc_co_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79699 { 25975 /* v_sub_co_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79700 { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79701 { 25975 /* v_sub_co_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79702 { 25975 /* v_sub_co_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79703 { 25975 /* v_sub_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79704 { 25975 /* v_sub_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79833 { 26090 /* v_sub_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79834 { 26090 /* v_sub_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79835 { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79836 { 26090 /* v_sub_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79837 { 26090 /* v_sub_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79838 { 26090 /* v_sub_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79851 { 26100 /* v_subb_co_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79852 { 26100 /* v_subb_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79853 { 26100 /* v_subb_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79854 { 26100 /* v_subb_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79855 { 26100 /* v_subb_co_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79856 { 26100 /* v_subb_co_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79877 { 26125 /* v_subbrev_co_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79878 { 26125 /* v_subbrev_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79879 { 26125 /* v_subbrev_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79880 { 26125 /* v_subbrev_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79881 { 26125 /* v_subbrev_co_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79882 { 26125 /* v_subbrev_co_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79946 { 26175 /* v_subrev_co_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79947 { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79948 { 26175 /* v_subrev_co_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79949 { 26175 /* v_subrev_co_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79950 { 26175 /* v_subrev_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79951 { 26175 /* v_subrev_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80076 { 26259 /* v_subrev_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80077 { 26259 /* v_subrev_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80078 { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80079 { 26259 /* v_subrev_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80080 { 26259 /* v_subrev_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80081 { 26259 /* v_subrev_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },