reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

23070   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23072   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23074   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23080   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23081   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23083   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23085   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23087   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23089   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23091   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23093   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23095   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23097   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23099   { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23101   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23103   { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23105   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23107   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23109   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23110   { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23112   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23113   { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23115   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23117   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23119   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23121   { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23123   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23125   { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23127   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23129   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23131   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23133   { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23135   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23137   { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23139   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23141   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23143   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23145   { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23147   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23149   { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23151   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23153   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23155   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23157   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23159   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23161   { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23163   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23165   { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23167   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23169   { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23171   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23173   { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23175   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23177   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23179   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23181   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23183   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23185   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23187   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23189   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23191   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23193   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23195   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23197   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23199   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23201   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23203   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23204   { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23206   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23207   { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23209   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23211   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23213   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23215   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23217   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23219   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23221   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23223   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23225   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23227   { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23229   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23231   { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23233   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23235   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23237   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23238   { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23240   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23241   { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23243   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23245   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23247   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23249   { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23251   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23253   { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23255   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23257   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23259   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23261   { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23263   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23265   { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23267   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23269   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23271   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23273   { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23275   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23277   { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23279   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23281   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23283   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23285   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23287   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23289   { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23291   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23293   { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23295   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23297   { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23299   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23301   { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23303   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23305   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23307   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23309   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23311   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23313   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23315   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23317   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23319   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23321   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23323   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23325   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23327   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23329   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23331   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23332   { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23334   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23335   { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23337   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23339   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23341   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23343   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23345   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23354   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23357   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23359   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23361   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23363   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23365   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23367   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23369   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23371   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23373   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23375   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23377   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23379   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23381   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23383   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23385   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23387   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23389   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23391   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23393   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23395   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23397   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23399   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23401   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23402   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23404   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23406   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23408   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23410   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23412   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23414   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23416   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23418   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23420   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23422   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23424   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23426   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23428   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23430   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23431   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23432   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23434   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23435   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23437   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23440   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23442   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23443   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23445   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23446   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23448   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23450   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23452   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23453   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23455   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23456   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23458   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23460   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23462   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23464   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23466   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23468   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23470   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23472   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23474   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23475   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23477   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23479   { 25176 /* v_nop */, AMDGPU::V_NOP_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, {  }, },
23481   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23483   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23486   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23488   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23490   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23492   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23494   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23496   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23498   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23500   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23501   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23503   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23505   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23507   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23509   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23519   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23521   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23523   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23540   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23542   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23544   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23547   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23549   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23553   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72935   { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
72936   { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
72937   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
72938   { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
72939   { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
72940   { 13251 /* v_add_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
72941   { 13251 /* v_add_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
72977   { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
72978   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
72979   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
72980   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
72981   { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
72982   { 13261 /* v_add_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
72983   { 13261 /* v_add_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73023   { 13368 /* v_add_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73024   { 13368 /* v_add_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73025   { 13368 /* v_add_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73026   { 13368 /* v_add_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73027   { 13368 /* v_add_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73028   { 13368 /* v_add_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73101   { 13444 /* v_and_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73102   { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73103   { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73104   { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73105   { 13444 /* v_and_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73106   { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73117   { 13489 /* v_ashrrev_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73118   { 13489 /* v_ashrrev_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73119   { 13489 /* v_ashrrev_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73120   { 13489 /* v_ashrrev_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73121   { 13489 /* v_ashrrev_i16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73122   { 13489 /* v_ashrrev_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73146   { 13503 /* v_ashrrev_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73147   { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73148   { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73149   { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73150   { 13503 /* v_ashrrev_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73151   { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73168   { 13586 /* v_bfrev_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73169   { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73170   { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73171   { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73172   { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73202   { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73203   { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
73204   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73205   { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73206   { 13598 /* v_ceil_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73207   { 13598 /* v_ceil_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73241   { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73242   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
73243   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73244   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73245   { 13609 /* v_ceil_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73246   { 13609 /* v_ceil_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
73271   { 13641 /* v_cmp_class_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73272   { 13641 /* v_cmp_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73273   { 13641 /* v_cmp_class_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73274   { 13641 /* v_cmp_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73275   { 13641 /* v_cmp_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73292   { 13677 /* v_cmp_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73293   { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73294   { 13677 /* v_cmp_class_f32 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73295   { 13677 /* v_cmp_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73296   { 13677 /* v_cmp_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73318   { 13749 /* v_cmp_eq_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73319   { 13749 /* v_cmp_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73320   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73321   { 13749 /* v_cmp_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73339   { 13779 /* v_cmp_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73340   { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73341   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73342   { 13779 /* v_cmp_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73362   { 13839 /* v_cmp_eq_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73363   { 13839 /* v_cmp_eq_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73364   { 13839 /* v_cmp_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73365   { 13839 /* v_cmp_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73377   { 13869 /* v_cmp_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73378   { 13869 /* v_cmp_eq_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73379   { 13869 /* v_cmp_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73380   { 13869 /* v_cmp_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73394   { 13929 /* v_cmp_eq_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73395   { 13929 /* v_cmp_eq_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73396   { 13929 /* v_cmp_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73397   { 13929 /* v_cmp_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73409   { 13959 /* v_cmp_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73410   { 13959 /* v_cmp_eq_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73411   { 13959 /* v_cmp_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73412   { 13959 /* v_cmp_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73430   { 14019 /* v_cmp_f_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73431   { 14019 /* v_cmp_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73432   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73433   { 14019 /* v_cmp_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73451   { 14047 /* v_cmp_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73452   { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73453   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73454   { 14047 /* v_cmp_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73469   { 14103 /* v_cmp_f_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73470   { 14103 /* v_cmp_f_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73471   { 14103 /* v_cmp_f_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73472   { 14103 /* v_cmp_f_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73484   { 14131 /* v_cmp_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73485   { 14131 /* v_cmp_f_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73486   { 14131 /* v_cmp_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73487   { 14131 /* v_cmp_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73496   { 14187 /* v_cmp_f_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73497   { 14187 /* v_cmp_f_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73498   { 14187 /* v_cmp_f_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73499   { 14187 /* v_cmp_f_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73511   { 14215 /* v_cmp_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73512   { 14215 /* v_cmp_f_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73513   { 14215 /* v_cmp_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73514   { 14215 /* v_cmp_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73532   { 14271 /* v_cmp_ge_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73533   { 14271 /* v_cmp_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73534   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73535   { 14271 /* v_cmp_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73553   { 14301 /* v_cmp_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73554   { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73555   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73556   { 14301 /* v_cmp_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73576   { 14361 /* v_cmp_ge_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73577   { 14361 /* v_cmp_ge_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73578   { 14361 /* v_cmp_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73579   { 14361 /* v_cmp_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73591   { 14391 /* v_cmp_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73592   { 14391 /* v_cmp_ge_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73593   { 14391 /* v_cmp_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73594   { 14391 /* v_cmp_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73608   { 14451 /* v_cmp_ge_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73609   { 14451 /* v_cmp_ge_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73610   { 14451 /* v_cmp_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73611   { 14451 /* v_cmp_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73623   { 14481 /* v_cmp_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73624   { 14481 /* v_cmp_ge_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73625   { 14481 /* v_cmp_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73626   { 14481 /* v_cmp_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73644   { 14541 /* v_cmp_gt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73645   { 14541 /* v_cmp_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73646   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73647   { 14541 /* v_cmp_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73665   { 14571 /* v_cmp_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73666   { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73667   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73668   { 14571 /* v_cmp_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73688   { 14631 /* v_cmp_gt_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73689   { 14631 /* v_cmp_gt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73690   { 14631 /* v_cmp_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73691   { 14631 /* v_cmp_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73703   { 14661 /* v_cmp_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73704   { 14661 /* v_cmp_gt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73705   { 14661 /* v_cmp_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73706   { 14661 /* v_cmp_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73720   { 14721 /* v_cmp_gt_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73721   { 14721 /* v_cmp_gt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73722   { 14721 /* v_cmp_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73723   { 14721 /* v_cmp_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73735   { 14751 /* v_cmp_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73736   { 14751 /* v_cmp_gt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73737   { 14751 /* v_cmp_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73738   { 14751 /* v_cmp_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73756   { 14811 /* v_cmp_le_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73757   { 14811 /* v_cmp_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73758   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73759   { 14811 /* v_cmp_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73777   { 14841 /* v_cmp_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73778   { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73779   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73780   { 14841 /* v_cmp_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73800   { 14901 /* v_cmp_le_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73801   { 14901 /* v_cmp_le_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73802   { 14901 /* v_cmp_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73803   { 14901 /* v_cmp_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73815   { 14931 /* v_cmp_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73816   { 14931 /* v_cmp_le_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73817   { 14931 /* v_cmp_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73818   { 14931 /* v_cmp_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73832   { 14991 /* v_cmp_le_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73833   { 14991 /* v_cmp_le_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73834   { 14991 /* v_cmp_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73835   { 14991 /* v_cmp_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73847   { 15021 /* v_cmp_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73848   { 15021 /* v_cmp_le_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73849   { 15021 /* v_cmp_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73850   { 15021 /* v_cmp_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73868   { 15081 /* v_cmp_lg_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73869   { 15081 /* v_cmp_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73870   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73871   { 15081 /* v_cmp_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73889   { 15111 /* v_cmp_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73890   { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73891   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73892   { 15111 /* v_cmp_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73916   { 15171 /* v_cmp_lt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73917   { 15171 /* v_cmp_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73918   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73919   { 15171 /* v_cmp_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73937   { 15201 /* v_cmp_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73938   { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73939   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73940   { 15201 /* v_cmp_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73960   { 15261 /* v_cmp_lt_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73961   { 15261 /* v_cmp_lt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73962   { 15261 /* v_cmp_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73963   { 15261 /* v_cmp_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73975   { 15291 /* v_cmp_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73976   { 15291 /* v_cmp_lt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73977   { 15291 /* v_cmp_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73978   { 15291 /* v_cmp_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
73992   { 15351 /* v_cmp_lt_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
73993   { 15351 /* v_cmp_lt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73994   { 15351 /* v_cmp_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73995   { 15351 /* v_cmp_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74007   { 15381 /* v_cmp_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74008   { 15381 /* v_cmp_lt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74009   { 15381 /* v_cmp_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74010   { 15381 /* v_cmp_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74024   { 15441 /* v_cmp_ne_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74025   { 15441 /* v_cmp_ne_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74026   { 15441 /* v_cmp_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74027   { 15441 /* v_cmp_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74039   { 15471 /* v_cmp_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74040   { 15471 /* v_cmp_ne_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74041   { 15471 /* v_cmp_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74042   { 15471 /* v_cmp_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74056   { 15531 /* v_cmp_ne_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74057   { 15531 /* v_cmp_ne_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74058   { 15531 /* v_cmp_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74059   { 15531 /* v_cmp_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74071   { 15561 /* v_cmp_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74072   { 15561 /* v_cmp_ne_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74073   { 15561 /* v_cmp_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74074   { 15561 /* v_cmp_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74092   { 15621 /* v_cmp_neq_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74093   { 15621 /* v_cmp_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74094   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74095   { 15621 /* v_cmp_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74113   { 15653 /* v_cmp_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74114   { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74115   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74116   { 15653 /* v_cmp_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74140   { 15717 /* v_cmp_nge_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74141   { 15717 /* v_cmp_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74142   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74143   { 15717 /* v_cmp_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74161   { 15749 /* v_cmp_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74162   { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74163   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74164   { 15749 /* v_cmp_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74188   { 15813 /* v_cmp_ngt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74189   { 15813 /* v_cmp_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74190   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74191   { 15813 /* v_cmp_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74209   { 15845 /* v_cmp_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74210   { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74211   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74212   { 15845 /* v_cmp_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74236   { 15909 /* v_cmp_nle_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74237   { 15909 /* v_cmp_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74238   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74239   { 15909 /* v_cmp_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74257   { 15941 /* v_cmp_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74258   { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74259   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74260   { 15941 /* v_cmp_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74284   { 16005 /* v_cmp_nlg_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74285   { 16005 /* v_cmp_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74286   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74287   { 16005 /* v_cmp_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74305   { 16037 /* v_cmp_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74306   { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74307   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74308   { 16037 /* v_cmp_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74332   { 16101 /* v_cmp_nlt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74333   { 16101 /* v_cmp_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74334   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74335   { 16101 /* v_cmp_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74353   { 16133 /* v_cmp_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74354   { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74355   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74356   { 16133 /* v_cmp_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74380   { 16197 /* v_cmp_o_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74381   { 16197 /* v_cmp_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74382   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74383   { 16197 /* v_cmp_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74401   { 16225 /* v_cmp_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74402   { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74403   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74404   { 16225 /* v_cmp_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74419   { 16281 /* v_cmp_t_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74420   { 16281 /* v_cmp_t_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74421   { 16281 /* v_cmp_t_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74422   { 16281 /* v_cmp_t_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74434   { 16309 /* v_cmp_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74435   { 16309 /* v_cmp_t_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74436   { 16309 /* v_cmp_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74437   { 16309 /* v_cmp_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74446   { 16365 /* v_cmp_t_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74447   { 16365 /* v_cmp_t_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74448   { 16365 /* v_cmp_t_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74449   { 16365 /* v_cmp_t_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74461   { 16393 /* v_cmp_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74462   { 16393 /* v_cmp_t_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74463   { 16393 /* v_cmp_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74464   { 16393 /* v_cmp_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74482   { 16449 /* v_cmp_tru_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74483   { 16449 /* v_cmp_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74484   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74485   { 16449 /* v_cmp_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74503   { 16481 /* v_cmp_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74504   { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74505   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74506   { 16481 /* v_cmp_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74530   { 16545 /* v_cmp_u_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74531   { 16545 /* v_cmp_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74532   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74533   { 16545 /* v_cmp_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74551   { 16573 /* v_cmp_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74552   { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74553   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74554   { 16573 /* v_cmp_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74767   { 18773 /* v_cmpx_class_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74768   { 18773 /* v_cmpx_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74769   { 18773 /* v_cmpx_class_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74770   { 18773 /* v_cmpx_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74771   { 18773 /* v_cmpx_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74786   { 18811 /* v_cmpx_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74787   { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74788   { 18811 /* v_cmpx_class_f32 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74789   { 18811 /* v_cmpx_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74790   { 18811 /* v_cmpx_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74809   { 18887 /* v_cmpx_eq_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74810   { 18887 /* v_cmpx_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74811   { 18887 /* v_cmpx_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74812   { 18887 /* v_cmpx_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74828   { 18919 /* v_cmpx_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74829   { 18919 /* v_cmpx_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74830   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74831   { 18919 /* v_cmpx_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74848   { 18983 /* v_cmpx_eq_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74849   { 18983 /* v_cmpx_eq_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74850   { 18983 /* v_cmpx_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74851   { 18983 /* v_cmpx_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74861   { 19015 /* v_cmpx_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74862   { 19015 /* v_cmpx_eq_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74863   { 19015 /* v_cmpx_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74864   { 19015 /* v_cmpx_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74875   { 19079 /* v_cmpx_eq_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74876   { 19079 /* v_cmpx_eq_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74877   { 19079 /* v_cmpx_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74878   { 19079 /* v_cmpx_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74888   { 19111 /* v_cmpx_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74889   { 19111 /* v_cmpx_eq_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74890   { 19111 /* v_cmpx_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74891   { 19111 /* v_cmpx_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74906   { 19175 /* v_cmpx_f_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74907   { 19175 /* v_cmpx_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74908   { 19175 /* v_cmpx_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74909   { 19175 /* v_cmpx_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74925   { 19205 /* v_cmpx_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74926   { 19205 /* v_cmpx_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74927   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74928   { 19205 /* v_cmpx_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74942   { 19265 /* v_cmpx_f_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74943   { 19265 /* v_cmpx_f_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74944   { 19265 /* v_cmpx_f_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74945   { 19265 /* v_cmpx_f_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74955   { 19295 /* v_cmpx_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74956   { 19295 /* v_cmpx_f_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74957   { 19295 /* v_cmpx_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74958   { 19295 /* v_cmpx_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74966   { 19355 /* v_cmpx_f_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74967   { 19355 /* v_cmpx_f_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74968   { 19355 /* v_cmpx_f_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74969   { 19355 /* v_cmpx_f_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74979   { 19385 /* v_cmpx_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74980   { 19385 /* v_cmpx_f_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74981   { 19385 /* v_cmpx_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74982   { 19385 /* v_cmpx_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
74997   { 19445 /* v_cmpx_ge_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
74998   { 19445 /* v_cmpx_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74999   { 19445 /* v_cmpx_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75000   { 19445 /* v_cmpx_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75016   { 19477 /* v_cmpx_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75017   { 19477 /* v_cmpx_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75018   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75019   { 19477 /* v_cmpx_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75036   { 19541 /* v_cmpx_ge_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75037   { 19541 /* v_cmpx_ge_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75038   { 19541 /* v_cmpx_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75039   { 19541 /* v_cmpx_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75049   { 19573 /* v_cmpx_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75050   { 19573 /* v_cmpx_ge_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75051   { 19573 /* v_cmpx_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75052   { 19573 /* v_cmpx_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75063   { 19637 /* v_cmpx_ge_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75064   { 19637 /* v_cmpx_ge_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75065   { 19637 /* v_cmpx_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75066   { 19637 /* v_cmpx_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75076   { 19669 /* v_cmpx_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75077   { 19669 /* v_cmpx_ge_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75078   { 19669 /* v_cmpx_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75079   { 19669 /* v_cmpx_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75094   { 19733 /* v_cmpx_gt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75095   { 19733 /* v_cmpx_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75096   { 19733 /* v_cmpx_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75097   { 19733 /* v_cmpx_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75113   { 19765 /* v_cmpx_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75114   { 19765 /* v_cmpx_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75115   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75116   { 19765 /* v_cmpx_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75133   { 19829 /* v_cmpx_gt_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75134   { 19829 /* v_cmpx_gt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75135   { 19829 /* v_cmpx_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75136   { 19829 /* v_cmpx_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75146   { 19861 /* v_cmpx_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75147   { 19861 /* v_cmpx_gt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75148   { 19861 /* v_cmpx_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75149   { 19861 /* v_cmpx_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75160   { 19925 /* v_cmpx_gt_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75161   { 19925 /* v_cmpx_gt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75162   { 19925 /* v_cmpx_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75163   { 19925 /* v_cmpx_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75173   { 19957 /* v_cmpx_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75174   { 19957 /* v_cmpx_gt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75175   { 19957 /* v_cmpx_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75176   { 19957 /* v_cmpx_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75191   { 20021 /* v_cmpx_le_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75192   { 20021 /* v_cmpx_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75193   { 20021 /* v_cmpx_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75194   { 20021 /* v_cmpx_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75210   { 20053 /* v_cmpx_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75211   { 20053 /* v_cmpx_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75212   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75213   { 20053 /* v_cmpx_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75230   { 20117 /* v_cmpx_le_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75231   { 20117 /* v_cmpx_le_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75232   { 20117 /* v_cmpx_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75233   { 20117 /* v_cmpx_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75243   { 20149 /* v_cmpx_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75244   { 20149 /* v_cmpx_le_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75245   { 20149 /* v_cmpx_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75246   { 20149 /* v_cmpx_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75257   { 20213 /* v_cmpx_le_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75258   { 20213 /* v_cmpx_le_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75259   { 20213 /* v_cmpx_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75260   { 20213 /* v_cmpx_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75270   { 20245 /* v_cmpx_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75271   { 20245 /* v_cmpx_le_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75272   { 20245 /* v_cmpx_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75273   { 20245 /* v_cmpx_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75288   { 20309 /* v_cmpx_lg_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75289   { 20309 /* v_cmpx_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75290   { 20309 /* v_cmpx_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75291   { 20309 /* v_cmpx_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75307   { 20341 /* v_cmpx_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75308   { 20341 /* v_cmpx_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75309   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75310   { 20341 /* v_cmpx_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75331   { 20405 /* v_cmpx_lt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75332   { 20405 /* v_cmpx_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75333   { 20405 /* v_cmpx_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75334   { 20405 /* v_cmpx_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75350   { 20437 /* v_cmpx_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75351   { 20437 /* v_cmpx_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75352   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75353   { 20437 /* v_cmpx_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75370   { 20501 /* v_cmpx_lt_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75371   { 20501 /* v_cmpx_lt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75372   { 20501 /* v_cmpx_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75373   { 20501 /* v_cmpx_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75383   { 20533 /* v_cmpx_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75384   { 20533 /* v_cmpx_lt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75385   { 20533 /* v_cmpx_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75386   { 20533 /* v_cmpx_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75397   { 20597 /* v_cmpx_lt_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75398   { 20597 /* v_cmpx_lt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75399   { 20597 /* v_cmpx_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75400   { 20597 /* v_cmpx_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75410   { 20629 /* v_cmpx_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75411   { 20629 /* v_cmpx_lt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75412   { 20629 /* v_cmpx_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75413   { 20629 /* v_cmpx_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75424   { 20693 /* v_cmpx_ne_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75425   { 20693 /* v_cmpx_ne_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75426   { 20693 /* v_cmpx_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75427   { 20693 /* v_cmpx_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75437   { 20725 /* v_cmpx_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75438   { 20725 /* v_cmpx_ne_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75439   { 20725 /* v_cmpx_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75440   { 20725 /* v_cmpx_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75451   { 20789 /* v_cmpx_ne_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75452   { 20789 /* v_cmpx_ne_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75453   { 20789 /* v_cmpx_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75454   { 20789 /* v_cmpx_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75464   { 20821 /* v_cmpx_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75465   { 20821 /* v_cmpx_ne_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75466   { 20821 /* v_cmpx_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75467   { 20821 /* v_cmpx_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75482   { 20885 /* v_cmpx_neq_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75483   { 20885 /* v_cmpx_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75484   { 20885 /* v_cmpx_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75485   { 20885 /* v_cmpx_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75501   { 20919 /* v_cmpx_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75502   { 20919 /* v_cmpx_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75503   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75504   { 20919 /* v_cmpx_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75525   { 20987 /* v_cmpx_nge_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75526   { 20987 /* v_cmpx_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75527   { 20987 /* v_cmpx_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75528   { 20987 /* v_cmpx_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75544   { 21021 /* v_cmpx_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75545   { 21021 /* v_cmpx_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75546   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75547   { 21021 /* v_cmpx_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75568   { 21089 /* v_cmpx_ngt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75569   { 21089 /* v_cmpx_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75570   { 21089 /* v_cmpx_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75571   { 21089 /* v_cmpx_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75587   { 21123 /* v_cmpx_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75588   { 21123 /* v_cmpx_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75589   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75590   { 21123 /* v_cmpx_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75611   { 21191 /* v_cmpx_nle_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75612   { 21191 /* v_cmpx_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75613   { 21191 /* v_cmpx_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75614   { 21191 /* v_cmpx_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75630   { 21225 /* v_cmpx_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75631   { 21225 /* v_cmpx_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75632   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75633   { 21225 /* v_cmpx_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75654   { 21293 /* v_cmpx_nlg_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75655   { 21293 /* v_cmpx_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75656   { 21293 /* v_cmpx_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75657   { 21293 /* v_cmpx_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75673   { 21327 /* v_cmpx_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75674   { 21327 /* v_cmpx_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75675   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75676   { 21327 /* v_cmpx_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75697   { 21395 /* v_cmpx_nlt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75698   { 21395 /* v_cmpx_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75699   { 21395 /* v_cmpx_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75700   { 21395 /* v_cmpx_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75716   { 21429 /* v_cmpx_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75717   { 21429 /* v_cmpx_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75718   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75719   { 21429 /* v_cmpx_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75740   { 21497 /* v_cmpx_o_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75741   { 21497 /* v_cmpx_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75742   { 21497 /* v_cmpx_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75743   { 21497 /* v_cmpx_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75759   { 21527 /* v_cmpx_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75760   { 21527 /* v_cmpx_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75761   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75762   { 21527 /* v_cmpx_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75776   { 21587 /* v_cmpx_t_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75777   { 21587 /* v_cmpx_t_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75778   { 21587 /* v_cmpx_t_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75779   { 21587 /* v_cmpx_t_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75789   { 21617 /* v_cmpx_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75790   { 21617 /* v_cmpx_t_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75791   { 21617 /* v_cmpx_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75792   { 21617 /* v_cmpx_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75800   { 21677 /* v_cmpx_t_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75801   { 21677 /* v_cmpx_t_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75802   { 21677 /* v_cmpx_t_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75803   { 21677 /* v_cmpx_t_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75813   { 21707 /* v_cmpx_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75814   { 21707 /* v_cmpx_t_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75815   { 21707 /* v_cmpx_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75816   { 21707 /* v_cmpx_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75831   { 21767 /* v_cmpx_tru_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75832   { 21767 /* v_cmpx_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75833   { 21767 /* v_cmpx_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75834   { 21767 /* v_cmpx_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75850   { 21801 /* v_cmpx_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75851   { 21801 /* v_cmpx_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75852   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75853   { 21801 /* v_cmpx_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75874   { 21869 /* v_cmpx_u_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75875   { 21869 /* v_cmpx_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75876   { 21869 /* v_cmpx_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75877   { 21869 /* v_cmpx_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75893   { 21899 /* v_cmpx_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA9_HasSDWA9 },
75894   { 21899 /* v_cmpx_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75895   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75896   { 21899 /* v_cmpx_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75958   { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75959   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
75960   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
75961   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75962   { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
75963   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
75994   { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75995   { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
75996   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
75997   { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
75998   { 21973 /* v_cos_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75999   { 21973 /* v_cos_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76033   { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76034   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76035   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76036   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76037   { 21983 /* v_cos_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76038   { 21983 /* v_cos_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76108   { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76109   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76110   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76111   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76112   { 22045 /* v_cvt_f16_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76113   { 22045 /* v_cvt_f16_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76146   { 22059 /* v_cvt_f16_i16 */, 2 /* 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76147   { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76148   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76149   { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76150   { 22059 /* v_cvt_f16_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76151   { 22059 /* v_cvt_f16_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76178   { 22073 /* v_cvt_f16_u16 */, 2 /* 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76179   { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76180   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76181   { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76182   { 22073 /* v_cvt_f16_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76183   { 22073 /* v_cvt_f16_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76211   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76212   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76213   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76214   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76215   { 22087 /* v_cvt_f32_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76216   { 22087 /* v_cvt_f32_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76260   { 22115 /* v_cvt_f32_i32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76261   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76262   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76263   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76264   { 22115 /* v_cvt_f32_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76265   { 22115 /* v_cvt_f32_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76294   { 22129 /* v_cvt_f32_u32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76295   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76296   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76297   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76298   { 22129 /* v_cvt_f32_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76299   { 22129 /* v_cvt_f32_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76328   { 22143 /* v_cvt_f32_ubyte0 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76329   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76330   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76331   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76332   { 22143 /* v_cvt_f32_ubyte0 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76333   { 22143 /* v_cvt_f32_ubyte0 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76362   { 22160 /* v_cvt_f32_ubyte1 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76363   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76364   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76365   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76366   { 22160 /* v_cvt_f32_ubyte1 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76367   { 22160 /* v_cvt_f32_ubyte1 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76396   { 22177 /* v_cvt_f32_ubyte2 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76397   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76398   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76399   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76400   { 22177 /* v_cvt_f32_ubyte2 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76401   { 22177 /* v_cvt_f32_ubyte2 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76430   { 22194 /* v_cvt_f32_ubyte3 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76431   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76432   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76433   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76434   { 22194 /* v_cvt_f32_ubyte3 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76435   { 22194 /* v_cvt_f32_ubyte3 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76475   { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76476   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76477   { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76478   { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76479   { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76507   { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76508   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76509   { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76510   { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76511   { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76541   { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76542   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76543   { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76544   { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76545   { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76579   { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76580   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76581   { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76582   { 22313 /* v_cvt_norm_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76583   { 22313 /* v_cvt_norm_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76611   { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76612   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76613   { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76614   { 22332 /* v_cvt_norm_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76615   { 22332 /* v_cvt_norm_u16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76655   { 22351 /* v_cvt_off_f32_i4 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76656   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
76657   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76658   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76659   { 22351 /* v_cvt_off_f32_i4 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76660   { 22351 /* v_cvt_off_f32_i4 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76727   { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76728   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76729   { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76730   { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76731   { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76759   { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76760   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76761   { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76762   { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76763   { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76793   { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76794   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76795   { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76796   { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76797   { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
76999   { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77000   { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77001   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77002   { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77003   { 22899 /* v_exp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77004   { 22899 /* v_exp_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77038   { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77039   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77040   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77041   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77042   { 22909 /* v_exp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77043   { 22909 /* v_exp_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77066   { 22919 /* v_exp_legacy_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77067   { 22919 /* v_exp_legacy_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77068   { 22919 /* v_exp_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77069   { 22919 /* v_exp_legacy_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77070   { 22919 /* v_exp_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77071   { 22919 /* v_exp_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77088   { 22936 /* v_ffbh_i32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77089   { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77090   { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77091   { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77092   { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77114   { 22947 /* v_ffbh_u32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77115   { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77116   { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77117   { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77118   { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77140   { 22958 /* v_ffbl_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77141   { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77142   { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77143   { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77144   { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77174   { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77175   { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77176   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77177   { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77178   { 22969 /* v_floor_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77179   { 22969 /* v_floor_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77213   { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77214   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77215   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77216   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77217   { 22981 /* v_floor_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77218   { 22981 /* v_floor_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77352   { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77353   { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77354   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77355   { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77356   { 23168 /* v_fract_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77357   { 23168 /* v_fract_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77391   { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77392   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77393   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77394   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77395   { 23180 /* v_fract_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77396   { 23180 /* v_fract_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77428   { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77429   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77430   { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77431   { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77432   { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77462   { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77463   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77464   { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77465   { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77466   { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77508   { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77509   { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77510   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77511   { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77512   { 23264 /* v_frexp_mant_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77513   { 23264 /* v_frexp_mant_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77547   { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77548   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77549   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77550   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77551   { 23281 /* v_frexp_mant_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77552   { 23281 /* v_frexp_mant_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77683   { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77684   { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77685   { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77686   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77687   { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77688   { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77689   { 23439 /* v_ldexp_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
77690   { 23439 /* v_ldexp_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77742   { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77743   { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77744   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77745   { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77746   { 23501 /* v_log_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77747   { 23501 /* v_log_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77781   { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77782   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77783   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77784   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77785   { 23511 /* v_log_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77786   { 23511 /* v_log_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77809   { 23521 /* v_log_legacy_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77810   { 23521 /* v_log_legacy_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
77811   { 23521 /* v_log_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77812   { 23521 /* v_log_legacy_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77813   { 23521 /* v_log_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77814   { 23521 /* v_log_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77825   { 23589 /* v_lshlrev_b16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77826   { 23589 /* v_lshlrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77827   { 23589 /* v_lshlrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77828   { 23589 /* v_lshlrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77829   { 23589 /* v_lshlrev_b16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
77830   { 23589 /* v_lshlrev_b16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77854   { 23603 /* v_lshlrev_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77855   { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77856   { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77857   { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77858   { 23603 /* v_lshlrev_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
77859   { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77870   { 23653 /* v_lshrrev_b16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77871   { 23653 /* v_lshrrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77872   { 23653 /* v_lshrrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77873   { 23653 /* v_lshrrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77874   { 23653 /* v_lshrrev_b16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
77875   { 23653 /* v_lshrrev_b16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
77899   { 23667 /* v_lshrrev_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77900   { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77901   { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77902   { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77903   { 23667 /* v_lshrrev_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
77904   { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78108   { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78109   { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78110   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78111   { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78112   { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78113   { 24084 /* v_max_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78114   { 24084 /* v_max_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78150   { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78151   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78152   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78153   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78154   { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78155   { 24094 /* v_max_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78156   { 24094 /* v_max_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78176   { 24114 /* v_max_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78177   { 24114 /* v_max_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78178   { 24114 /* v_max_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78179   { 24114 /* v_max_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78180   { 24114 /* v_max_i16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78181   { 24114 /* v_max_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78205   { 24124 /* v_max_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78206   { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78207   { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78208   { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78209   { 24124 /* v_max_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78210   { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78224   { 24151 /* v_max_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78225   { 24151 /* v_max_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78226   { 24151 /* v_max_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78227   { 24151 /* v_max_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78228   { 24151 /* v_max_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78229   { 24151 /* v_max_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78253   { 24161 /* v_max_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78254   { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78255   { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78256   { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78257   { 24161 /* v_max_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78258   { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78397   { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78398   { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78399   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78400   { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78401   { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78402   { 24775 /* v_min_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78403   { 24775 /* v_min_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78439   { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78440   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78441   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78442   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78443   { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78444   { 24785 /* v_min_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78445   { 24785 /* v_min_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78465   { 24805 /* v_min_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78466   { 24805 /* v_min_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78467   { 24805 /* v_min_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78468   { 24805 /* v_min_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78469   { 24805 /* v_min_i16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78470   { 24805 /* v_min_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78494   { 24815 /* v_min_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78495   { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78496   { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78497   { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78498   { 24815 /* v_min_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78499   { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78513   { 24842 /* v_min_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78514   { 24842 /* v_min_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78515   { 24842 /* v_min_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78516   { 24842 /* v_min_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78517   { 24842 /* v_min_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78518   { 24842 /* v_min_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78542   { 24852 /* v_min_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78543   { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78544   { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78545   { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78546   { 24852 /* v_min_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78547   { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78564   { 24862 /* v_mov_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78565   { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78566   { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78567   { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78568   { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78590   { 24872 /* v_mov_fed_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78591   { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78592   { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78593   { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78594   { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78641   { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78642   { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78643   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78644   { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78645   { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78646   { 24989 /* v_mul_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78647   { 24989 /* v_mul_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78683   { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78684   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78685   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78686   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78687   { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78688   { 24999 /* v_mul_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78689   { 24999 /* v_mul_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78722   { 25032 /* v_mul_hi_i32_i24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78723   { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78724   { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78725   { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78726   { 25032 /* v_mul_hi_i32_i24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78727   { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78751   { 25062 /* v_mul_hi_u32_u24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78752   { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78753   { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78754   { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78755   { 25062 /* v_mul_hi_u32_u24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78756   { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78780   { 25079 /* v_mul_i32_i24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78781   { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78782   { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78783   { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78784   { 25079 /* v_mul_i32_i24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78785   { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78821   { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78822   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
78823   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78824   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78825   { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78826   { 25093 /* v_mul_legacy_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78827   { 25093 /* v_mul_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78838   { 25123 /* v_mul_lo_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78839   { 25123 /* v_mul_lo_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78840   { 25123 /* v_mul_lo_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78841   { 25123 /* v_mul_lo_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78842   { 25123 /* v_mul_lo_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78843   { 25123 /* v_mul_lo_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78867   { 25149 /* v_mul_u32_u24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78868   { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78869   { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78870   { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78871   { 25149 /* v_mul_u32_u24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78872   { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78895   { 25182 /* v_not_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78896   { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78897   { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78898   { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78899   { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
78928   { 25202 /* v_or_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78929   { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78930   { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78931   { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78932   { 25202 /* v_or_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
78933   { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79165   { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79166   { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79167   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79168   { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79169   { 25609 /* v_rcp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79170   { 25609 /* v_rcp_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79204   { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79205   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79206   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79207   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79208   { 25619 /* v_rcp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79209   { 25619 /* v_rcp_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79252   { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79253   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79254   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79255   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79256   { 25639 /* v_rcp_iflag_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79257   { 25639 /* v_rcp_iflag_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79291   { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79292   { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79293   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79294   { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79295   { 25707 /* v_rndne_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79296   { 25707 /* v_rndne_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79330   { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79331   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79332   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79333   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79334   { 25719 /* v_rndne_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79335   { 25719 /* v_rndne_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79381   { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79382   { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79383   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79384   { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79385   { 25775 /* v_rsq_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79386   { 25775 /* v_rsq_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79420   { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79421   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79422   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79423   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79424   { 25785 /* v_rsq_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79425   { 25785 /* v_rsq_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79472   { 25863 /* v_sat_pk_u8_i16 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79473   { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79474   { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79475   { 25863 /* v_sat_pk_u8_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79476   { 25863 /* v_sat_pk_u8_i16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79486   { 25879 /* v_screen_partition_4se_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79487   { 25879 /* v_screen_partition_4se_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79488   { 25879 /* v_screen_partition_4se_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79489   { 25879 /* v_screen_partition_4se_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79490   { 25879 /* v_screen_partition_4se_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79515   { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79516   { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79517   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79518   { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79519   { 25906 /* v_sin_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79520   { 25906 /* v_sin_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79554   { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79555   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79556   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79557   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79558   { 25916 /* v_sin_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79559   { 25916 /* v_sin_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79590   { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79591   { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79592   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79593   { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79594   { 25926 /* v_sqrt_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79595   { 25926 /* v_sqrt_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79629   { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79630   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79631   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79632   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79633   { 25937 /* v_sqrt_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79634   { 25937 /* v_sqrt_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79737   { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79738   { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79739   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79740   { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79741   { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79742   { 25988 /* v_sub_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
79743   { 25988 /* v_sub_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79779   { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79780   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79781   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79782   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79783   { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79784   { 25998 /* v_sub_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
79785   { 25998 /* v_sub_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79816   { 26080 /* v_sub_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79817   { 26080 /* v_sub_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79818   { 26080 /* v_sub_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79819   { 26080 /* v_sub_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79820   { 26080 /* v_sub_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
79821   { 26080 /* v_sub_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
79984   { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79985   { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
79986   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79987   { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79988   { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79989   { 26191 /* v_subrev_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
79990   { 26191 /* v_subrev_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
80026   { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80027   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
80028   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80029   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80030   { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80031   { 26204 /* v_subrev_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
80032   { 26204 /* v_subrev_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
80059   { 26246 /* v_subrev_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80060   { 26246 /* v_subrev_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80061   { 26246 /* v_subrev_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80062   { 26246 /* v_subrev_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80063   { 26246 /* v_subrev_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
80064   { 26246 /* v_subrev_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
80124   { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80125   { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
80126   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80127   { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80128   { 26314 /* v_trunc_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80129   { 26314 /* v_trunc_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
80163   { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80164   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA9_HasSDWA9 },
80165   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80166   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80167   { 26326 /* v_trunc_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80168   { 26326 /* v_trunc_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },
80236   { 26398 /* v_xor_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80237   { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80238   { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80239   { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80240   { 26398 /* v_xor_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA9_HasSDWA9 },
80241   { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA9_HasSDWA9 },