reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23065 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23355 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23514 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 23535 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, }, 72883 { 13222 /* v_add_co_ci_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 72884 { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 72885 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 72886 { 13222 /* v_add_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 72887 { 13222 /* v_add_co_ci_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 72888 { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 75964 { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 75965 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 75966 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 75967 { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 75968 { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 75969 { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79685 { 25959 /* v_sub_co_ci_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79686 { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79687 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79688 { 25959 /* v_sub_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79689 { 25959 /* v_sub_co_ci_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79690 { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79932 { 26156 /* v_subrev_co_ci_u32 */, 12 /* 2, 3 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79933 { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79934 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79935 { 26156 /* v_subrev_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79936 { 26156 /* v_subrev_co_ci_u32 */, 512 /* 9 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 }, 79937 { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },