reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

23063   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23069   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23071   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23073   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23079   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23082   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23084   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23086   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23088   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23090   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23092   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23094   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23096   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23098   { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23100   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23102   { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23104   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23106   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23108   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23111   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23114   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23116   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23118   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23120   { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23122   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23124   { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23126   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23128   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23130   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23132   { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23134   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23136   { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23138   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23140   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23142   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23144   { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23146   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23148   { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23150   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23152   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23154   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23156   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23158   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23160   { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23162   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23164   { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23166   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23168   { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23170   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23172   { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23174   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23176   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23178   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23180   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23182   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23184   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23186   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23188   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23190   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23192   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23194   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23196   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23198   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23200   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23202   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23205   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23208   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23210   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23212   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23214   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23216   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23218   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23220   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23222   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23224   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23226   { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23228   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23230   { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23232   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23234   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23236   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23239   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23242   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23244   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23246   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23248   { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23250   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23252   { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23254   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23256   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23258   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23260   { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23262   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23264   { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23266   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23268   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23270   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23272   { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23274   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23276   { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23278   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23280   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23282   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23284   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23286   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23288   { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23290   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23292   { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23294   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23296   { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23298   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23300   { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23302   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23304   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23306   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23308   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23310   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23312   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23314   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23316   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23318   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23320   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23322   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23324   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23326   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23328   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23330   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23333   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23336   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23338   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23340   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23342   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23344   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23352   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23356   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23358   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23360   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23362   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23364   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23366   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23368   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23370   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23372   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23374   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23376   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23378   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23380   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23382   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23384   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23386   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23388   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23390   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23392   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23394   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23396   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23398   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23400   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23403   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23405   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23407   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23409   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23411   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23413   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23415   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23417   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23419   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23421   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23423   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23425   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23427   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23429   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23433   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23436   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23438   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23439   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23441   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23444   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23447   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23449   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23451   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23454   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23457   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23459   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23461   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23463   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23465   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23467   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23469   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23471   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23473   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23476   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23478   { 25176 /* v_nop */, AMDGPU::V_NOP_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, {  }, },
23480   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23482   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23484   { 25272 /* v_pipeflush */, AMDGPU::V_PIPEFLUSH_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, {  }, },
23485   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23487   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23489   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23491   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23493   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23495   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23497   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23499   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23502   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23504   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23506   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23508   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23512   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23518   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23520   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23522   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23533   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23539   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23541   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23543   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23546   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23548   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23550   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23552   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72861   { 13222 /* v_add_co_ci_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
72862   { 13222 /* v_add_co_ci_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
72863   { 13222 /* v_add_co_ci_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
72864   { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
72865   { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
72866   { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
72928   { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
72929   { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
72930   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
72931   { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
72932   { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
72933   { 13251 /* v_add_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
72934   { 13251 /* v_add_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
72970   { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
72971   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
72972   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
72973   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
72974   { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
72975   { 13261 /* v_add_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
72976   { 13261 /* v_add_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73007   { 13355 /* v_add_nc_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73008   { 13355 /* v_add_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73009   { 13355 /* v_add_nc_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73010   { 13355 /* v_add_nc_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73011   { 13355 /* v_add_nc_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73012   { 13355 /* v_add_nc_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73095   { 13444 /* v_and_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73096   { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73097   { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73098   { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73099   { 13444 /* v_and_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73100   { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73140   { 13503 /* v_ashrrev_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73141   { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73142   { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73143   { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73144   { 13503 /* v_ashrrev_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73145   { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73163   { 13586 /* v_bfrev_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73164   { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73165   { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73166   { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73167   { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73196   { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73197   { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
73198   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73199   { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73200   { 13598 /* v_ceil_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73201   { 13598 /* v_ceil_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73235   { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73236   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
73237   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73238   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73239   { 13609 /* v_ceil_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73240   { 13609 /* v_ceil_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
73266   { 13641 /* v_cmp_class_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73267   { 13641 /* v_cmp_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73268   { 13641 /* v_cmp_class_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73269   { 13641 /* v_cmp_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73270   { 13641 /* v_cmp_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73287   { 13677 /* v_cmp_class_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73288   { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73289   { 13677 /* v_cmp_class_f32 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73290   { 13677 /* v_cmp_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73291   { 13677 /* v_cmp_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73314   { 13749 /* v_cmp_eq_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73315   { 13749 /* v_cmp_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73316   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73317   { 13749 /* v_cmp_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73335   { 13779 /* v_cmp_eq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73336   { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73337   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73338   { 13779 /* v_cmp_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73358   { 13839 /* v_cmp_eq_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73359   { 13839 /* v_cmp_eq_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73360   { 13839 /* v_cmp_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73361   { 13839 /* v_cmp_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73373   { 13869 /* v_cmp_eq_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73374   { 13869 /* v_cmp_eq_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73375   { 13869 /* v_cmp_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73376   { 13869 /* v_cmp_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73390   { 13929 /* v_cmp_eq_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73391   { 13929 /* v_cmp_eq_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73392   { 13929 /* v_cmp_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73393   { 13929 /* v_cmp_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73405   { 13959 /* v_cmp_eq_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73406   { 13959 /* v_cmp_eq_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73407   { 13959 /* v_cmp_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73408   { 13959 /* v_cmp_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73426   { 14019 /* v_cmp_f_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73427   { 14019 /* v_cmp_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73428   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73429   { 14019 /* v_cmp_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73447   { 14047 /* v_cmp_f_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73448   { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73449   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73450   { 14047 /* v_cmp_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73480   { 14131 /* v_cmp_f_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73481   { 14131 /* v_cmp_f_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73482   { 14131 /* v_cmp_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73483   { 14131 /* v_cmp_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73507   { 14215 /* v_cmp_f_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73508   { 14215 /* v_cmp_f_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73509   { 14215 /* v_cmp_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73510   { 14215 /* v_cmp_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73528   { 14271 /* v_cmp_ge_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73529   { 14271 /* v_cmp_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73530   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73531   { 14271 /* v_cmp_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73549   { 14301 /* v_cmp_ge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73550   { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73551   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73552   { 14301 /* v_cmp_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73572   { 14361 /* v_cmp_ge_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73573   { 14361 /* v_cmp_ge_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73574   { 14361 /* v_cmp_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73575   { 14361 /* v_cmp_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73587   { 14391 /* v_cmp_ge_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73588   { 14391 /* v_cmp_ge_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73589   { 14391 /* v_cmp_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73590   { 14391 /* v_cmp_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73604   { 14451 /* v_cmp_ge_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73605   { 14451 /* v_cmp_ge_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73606   { 14451 /* v_cmp_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73607   { 14451 /* v_cmp_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73619   { 14481 /* v_cmp_ge_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73620   { 14481 /* v_cmp_ge_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73621   { 14481 /* v_cmp_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73622   { 14481 /* v_cmp_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73640   { 14541 /* v_cmp_gt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73641   { 14541 /* v_cmp_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73642   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73643   { 14541 /* v_cmp_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73661   { 14571 /* v_cmp_gt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73662   { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73663   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73664   { 14571 /* v_cmp_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73684   { 14631 /* v_cmp_gt_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73685   { 14631 /* v_cmp_gt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73686   { 14631 /* v_cmp_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73687   { 14631 /* v_cmp_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73699   { 14661 /* v_cmp_gt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73700   { 14661 /* v_cmp_gt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73701   { 14661 /* v_cmp_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73702   { 14661 /* v_cmp_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73716   { 14721 /* v_cmp_gt_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73717   { 14721 /* v_cmp_gt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73718   { 14721 /* v_cmp_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73719   { 14721 /* v_cmp_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73731   { 14751 /* v_cmp_gt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73732   { 14751 /* v_cmp_gt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73733   { 14751 /* v_cmp_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73734   { 14751 /* v_cmp_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73752   { 14811 /* v_cmp_le_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73753   { 14811 /* v_cmp_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73754   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73755   { 14811 /* v_cmp_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73773   { 14841 /* v_cmp_le_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73774   { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73775   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73776   { 14841 /* v_cmp_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73796   { 14901 /* v_cmp_le_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73797   { 14901 /* v_cmp_le_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73798   { 14901 /* v_cmp_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73799   { 14901 /* v_cmp_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73811   { 14931 /* v_cmp_le_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73812   { 14931 /* v_cmp_le_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73813   { 14931 /* v_cmp_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73814   { 14931 /* v_cmp_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73828   { 14991 /* v_cmp_le_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73829   { 14991 /* v_cmp_le_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73830   { 14991 /* v_cmp_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73831   { 14991 /* v_cmp_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73843   { 15021 /* v_cmp_le_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73844   { 15021 /* v_cmp_le_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73845   { 15021 /* v_cmp_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73846   { 15021 /* v_cmp_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73864   { 15081 /* v_cmp_lg_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73865   { 15081 /* v_cmp_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73866   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73867   { 15081 /* v_cmp_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73885   { 15111 /* v_cmp_lg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73886   { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73887   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73888   { 15111 /* v_cmp_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73912   { 15171 /* v_cmp_lt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73913   { 15171 /* v_cmp_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73914   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73915   { 15171 /* v_cmp_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73933   { 15201 /* v_cmp_lt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73934   { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73935   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73936   { 15201 /* v_cmp_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73956   { 15261 /* v_cmp_lt_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73957   { 15261 /* v_cmp_lt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73958   { 15261 /* v_cmp_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73959   { 15261 /* v_cmp_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73971   { 15291 /* v_cmp_lt_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73972   { 15291 /* v_cmp_lt_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73973   { 15291 /* v_cmp_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73974   { 15291 /* v_cmp_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
73988   { 15351 /* v_cmp_lt_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
73989   { 15351 /* v_cmp_lt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73990   { 15351 /* v_cmp_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73991   { 15351 /* v_cmp_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74003   { 15381 /* v_cmp_lt_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74004   { 15381 /* v_cmp_lt_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74005   { 15381 /* v_cmp_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74006   { 15381 /* v_cmp_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74020   { 15441 /* v_cmp_ne_i16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74021   { 15441 /* v_cmp_ne_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74022   { 15441 /* v_cmp_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74023   { 15441 /* v_cmp_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74035   { 15471 /* v_cmp_ne_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74036   { 15471 /* v_cmp_ne_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74037   { 15471 /* v_cmp_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74038   { 15471 /* v_cmp_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74052   { 15531 /* v_cmp_ne_u16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74053   { 15531 /* v_cmp_ne_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74054   { 15531 /* v_cmp_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74055   { 15531 /* v_cmp_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74067   { 15561 /* v_cmp_ne_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74068   { 15561 /* v_cmp_ne_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74069   { 15561 /* v_cmp_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74070   { 15561 /* v_cmp_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74088   { 15621 /* v_cmp_neq_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74089   { 15621 /* v_cmp_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74090   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74091   { 15621 /* v_cmp_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74109   { 15653 /* v_cmp_neq_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74110   { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74111   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74112   { 15653 /* v_cmp_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74136   { 15717 /* v_cmp_nge_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74137   { 15717 /* v_cmp_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74138   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74139   { 15717 /* v_cmp_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74157   { 15749 /* v_cmp_nge_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74158   { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74159   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74160   { 15749 /* v_cmp_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74184   { 15813 /* v_cmp_ngt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74185   { 15813 /* v_cmp_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74186   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74187   { 15813 /* v_cmp_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74205   { 15845 /* v_cmp_ngt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74206   { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74207   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74208   { 15845 /* v_cmp_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74232   { 15909 /* v_cmp_nle_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74233   { 15909 /* v_cmp_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74234   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74235   { 15909 /* v_cmp_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74253   { 15941 /* v_cmp_nle_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74254   { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74255   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74256   { 15941 /* v_cmp_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74280   { 16005 /* v_cmp_nlg_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74281   { 16005 /* v_cmp_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74282   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74283   { 16005 /* v_cmp_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74301   { 16037 /* v_cmp_nlg_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74302   { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74303   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74304   { 16037 /* v_cmp_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74328   { 16101 /* v_cmp_nlt_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74329   { 16101 /* v_cmp_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74330   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74331   { 16101 /* v_cmp_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74349   { 16133 /* v_cmp_nlt_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74350   { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74351   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74352   { 16133 /* v_cmp_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74376   { 16197 /* v_cmp_o_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74377   { 16197 /* v_cmp_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74378   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74379   { 16197 /* v_cmp_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74397   { 16225 /* v_cmp_o_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74398   { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74399   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74400   { 16225 /* v_cmp_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74430   { 16309 /* v_cmp_t_i32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74431   { 16309 /* v_cmp_t_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74432   { 16309 /* v_cmp_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74433   { 16309 /* v_cmp_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74457   { 16393 /* v_cmp_t_u32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74458   { 16393 /* v_cmp_t_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74459   { 16393 /* v_cmp_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74460   { 16393 /* v_cmp_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74478   { 16449 /* v_cmp_tru_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74479   { 16449 /* v_cmp_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74480   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74481   { 16449 /* v_cmp_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74499   { 16481 /* v_cmp_tru_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74500   { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74501   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74502   { 16481 /* v_cmp_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74526   { 16545 /* v_cmp_u_f16 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74527   { 16545 /* v_cmp_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74528   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74529   { 16545 /* v_cmp_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74547   { 16573 /* v_cmp_u_f32 */, 1 /* 0 */, MCK_BoolReg, AMFBS_HasSDWA10_isGFX10Plus },
74548   { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74549   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74550   { 16573 /* v_cmp_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74763   { 18773 /* v_cmpx_class_f16 */, 1 /* 0 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74764   { 18773 /* v_cmpx_class_f16 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74765   { 18773 /* v_cmpx_class_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74766   { 18773 /* v_cmpx_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74782   { 18811 /* v_cmpx_class_f32 */, 1 /* 0 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74783   { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74784   { 18811 /* v_cmpx_class_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74785   { 18811 /* v_cmpx_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74806   { 18887 /* v_cmpx_eq_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74807   { 18887 /* v_cmpx_eq_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74808   { 18887 /* v_cmpx_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74825   { 18919 /* v_cmpx_eq_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74826   { 18919 /* v_cmpx_eq_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74827   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74845   { 18983 /* v_cmpx_eq_i16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74846   { 18983 /* v_cmpx_eq_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74847   { 18983 /* v_cmpx_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74858   { 19015 /* v_cmpx_eq_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74859   { 19015 /* v_cmpx_eq_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74860   { 19015 /* v_cmpx_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74872   { 19079 /* v_cmpx_eq_u16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74873   { 19079 /* v_cmpx_eq_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74874   { 19079 /* v_cmpx_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74885   { 19111 /* v_cmpx_eq_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74886   { 19111 /* v_cmpx_eq_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74887   { 19111 /* v_cmpx_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74903   { 19175 /* v_cmpx_f_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74904   { 19175 /* v_cmpx_f_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74905   { 19175 /* v_cmpx_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74922   { 19205 /* v_cmpx_f_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74923   { 19205 /* v_cmpx_f_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74924   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74952   { 19295 /* v_cmpx_f_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74953   { 19295 /* v_cmpx_f_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74954   { 19295 /* v_cmpx_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74976   { 19385 /* v_cmpx_f_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74977   { 19385 /* v_cmpx_f_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74978   { 19385 /* v_cmpx_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
74994   { 19445 /* v_cmpx_ge_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74995   { 19445 /* v_cmpx_ge_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74996   { 19445 /* v_cmpx_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75013   { 19477 /* v_cmpx_ge_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75014   { 19477 /* v_cmpx_ge_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75015   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75033   { 19541 /* v_cmpx_ge_i16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75034   { 19541 /* v_cmpx_ge_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75035   { 19541 /* v_cmpx_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75046   { 19573 /* v_cmpx_ge_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75047   { 19573 /* v_cmpx_ge_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75048   { 19573 /* v_cmpx_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75060   { 19637 /* v_cmpx_ge_u16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75061   { 19637 /* v_cmpx_ge_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75062   { 19637 /* v_cmpx_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75073   { 19669 /* v_cmpx_ge_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75074   { 19669 /* v_cmpx_ge_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75075   { 19669 /* v_cmpx_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75091   { 19733 /* v_cmpx_gt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75092   { 19733 /* v_cmpx_gt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75093   { 19733 /* v_cmpx_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75110   { 19765 /* v_cmpx_gt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75111   { 19765 /* v_cmpx_gt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75112   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75130   { 19829 /* v_cmpx_gt_i16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75131   { 19829 /* v_cmpx_gt_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75132   { 19829 /* v_cmpx_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75143   { 19861 /* v_cmpx_gt_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75144   { 19861 /* v_cmpx_gt_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75145   { 19861 /* v_cmpx_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75157   { 19925 /* v_cmpx_gt_u16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75158   { 19925 /* v_cmpx_gt_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75159   { 19925 /* v_cmpx_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75170   { 19957 /* v_cmpx_gt_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75171   { 19957 /* v_cmpx_gt_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75172   { 19957 /* v_cmpx_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75188   { 20021 /* v_cmpx_le_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75189   { 20021 /* v_cmpx_le_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75190   { 20021 /* v_cmpx_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75207   { 20053 /* v_cmpx_le_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75208   { 20053 /* v_cmpx_le_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75209   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75227   { 20117 /* v_cmpx_le_i16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75228   { 20117 /* v_cmpx_le_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75229   { 20117 /* v_cmpx_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75240   { 20149 /* v_cmpx_le_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75241   { 20149 /* v_cmpx_le_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75242   { 20149 /* v_cmpx_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75254   { 20213 /* v_cmpx_le_u16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75255   { 20213 /* v_cmpx_le_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75256   { 20213 /* v_cmpx_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75267   { 20245 /* v_cmpx_le_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75268   { 20245 /* v_cmpx_le_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75269   { 20245 /* v_cmpx_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75285   { 20309 /* v_cmpx_lg_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75286   { 20309 /* v_cmpx_lg_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75287   { 20309 /* v_cmpx_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75304   { 20341 /* v_cmpx_lg_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75305   { 20341 /* v_cmpx_lg_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75306   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75328   { 20405 /* v_cmpx_lt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75329   { 20405 /* v_cmpx_lt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75330   { 20405 /* v_cmpx_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75347   { 20437 /* v_cmpx_lt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75348   { 20437 /* v_cmpx_lt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75349   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75367   { 20501 /* v_cmpx_lt_i16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75368   { 20501 /* v_cmpx_lt_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75369   { 20501 /* v_cmpx_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75380   { 20533 /* v_cmpx_lt_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75381   { 20533 /* v_cmpx_lt_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75382   { 20533 /* v_cmpx_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75394   { 20597 /* v_cmpx_lt_u16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75395   { 20597 /* v_cmpx_lt_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75396   { 20597 /* v_cmpx_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75407   { 20629 /* v_cmpx_lt_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75408   { 20629 /* v_cmpx_lt_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75409   { 20629 /* v_cmpx_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75421   { 20693 /* v_cmpx_ne_i16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75422   { 20693 /* v_cmpx_ne_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75423   { 20693 /* v_cmpx_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75434   { 20725 /* v_cmpx_ne_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75435   { 20725 /* v_cmpx_ne_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75436   { 20725 /* v_cmpx_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75448   { 20789 /* v_cmpx_ne_u16 */, 3 /* 0, 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75449   { 20789 /* v_cmpx_ne_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75450   { 20789 /* v_cmpx_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75461   { 20821 /* v_cmpx_ne_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75462   { 20821 /* v_cmpx_ne_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75463   { 20821 /* v_cmpx_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75479   { 20885 /* v_cmpx_neq_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75480   { 20885 /* v_cmpx_neq_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75481   { 20885 /* v_cmpx_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75498   { 20919 /* v_cmpx_neq_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75499   { 20919 /* v_cmpx_neq_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75500   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75522   { 20987 /* v_cmpx_nge_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75523   { 20987 /* v_cmpx_nge_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75524   { 20987 /* v_cmpx_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75541   { 21021 /* v_cmpx_nge_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75542   { 21021 /* v_cmpx_nge_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75543   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75565   { 21089 /* v_cmpx_ngt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75566   { 21089 /* v_cmpx_ngt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75567   { 21089 /* v_cmpx_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75584   { 21123 /* v_cmpx_ngt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75585   { 21123 /* v_cmpx_ngt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75586   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75608   { 21191 /* v_cmpx_nle_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75609   { 21191 /* v_cmpx_nle_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75610   { 21191 /* v_cmpx_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75627   { 21225 /* v_cmpx_nle_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75628   { 21225 /* v_cmpx_nle_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75629   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75651   { 21293 /* v_cmpx_nlg_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75652   { 21293 /* v_cmpx_nlg_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75653   { 21293 /* v_cmpx_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75670   { 21327 /* v_cmpx_nlg_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75671   { 21327 /* v_cmpx_nlg_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75672   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75694   { 21395 /* v_cmpx_nlt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75695   { 21395 /* v_cmpx_nlt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75696   { 21395 /* v_cmpx_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75713   { 21429 /* v_cmpx_nlt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75714   { 21429 /* v_cmpx_nlt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75715   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75737   { 21497 /* v_cmpx_o_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75738   { 21497 /* v_cmpx_o_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75739   { 21497 /* v_cmpx_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75756   { 21527 /* v_cmpx_o_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75757   { 21527 /* v_cmpx_o_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75758   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75786   { 21617 /* v_cmpx_t_i32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75787   { 21617 /* v_cmpx_t_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75788   { 21617 /* v_cmpx_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75810   { 21707 /* v_cmpx_t_u32 */, 3 /* 0, 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75811   { 21707 /* v_cmpx_t_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75812   { 21707 /* v_cmpx_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75828   { 21767 /* v_cmpx_tru_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75829   { 21767 /* v_cmpx_tru_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75830   { 21767 /* v_cmpx_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75847   { 21801 /* v_cmpx_tru_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75848   { 21801 /* v_cmpx_tru_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75849   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75871   { 21869 /* v_cmpx_u_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75872   { 21869 /* v_cmpx_u_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75873   { 21869 /* v_cmpx_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75890   { 21899 /* v_cmpx_u_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75891   { 21899 /* v_cmpx_u_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75892   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75930   { 21959 /* v_cndmask_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75931   { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
75932   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
75933   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75934   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
75935   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
75988   { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75989   { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
75990   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
75991   { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
75992   { 21973 /* v_cos_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75993   { 21973 /* v_cos_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76027   { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76028   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76029   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76030   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76031   { 21983 /* v_cos_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76032   { 21983 /* v_cos_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76102   { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76103   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76104   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76105   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76106   { 22045 /* v_cvt_f16_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76107   { 22045 /* v_cvt_f16_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76140   { 22059 /* v_cvt_f16_i16 */, 2 /* 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76141   { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76142   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76143   { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76144   { 22059 /* v_cvt_f16_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76145   { 22059 /* v_cvt_f16_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76172   { 22073 /* v_cvt_f16_u16 */, 2 /* 1 */, MCK_SDWAWithInt16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76173   { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76174   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76175   { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76176   { 22073 /* v_cvt_f16_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76177   { 22073 /* v_cvt_f16_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76205   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76206   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76207   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76208   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76209   { 22087 /* v_cvt_f32_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76210   { 22087 /* v_cvt_f32_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76254   { 22115 /* v_cvt_f32_i32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76255   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76256   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76257   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76258   { 22115 /* v_cvt_f32_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76259   { 22115 /* v_cvt_f32_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76288   { 22129 /* v_cvt_f32_u32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76289   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76290   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76291   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76292   { 22129 /* v_cvt_f32_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76293   { 22129 /* v_cvt_f32_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76322   { 22143 /* v_cvt_f32_ubyte0 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76323   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76324   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76325   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76326   { 22143 /* v_cvt_f32_ubyte0 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76327   { 22143 /* v_cvt_f32_ubyte0 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76356   { 22160 /* v_cvt_f32_ubyte1 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76357   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76358   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76359   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76360   { 22160 /* v_cvt_f32_ubyte1 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76361   { 22160 /* v_cvt_f32_ubyte1 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76390   { 22177 /* v_cvt_f32_ubyte2 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76391   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76392   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76393   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76394   { 22177 /* v_cvt_f32_ubyte2 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76395   { 22177 /* v_cvt_f32_ubyte2 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76424   { 22194 /* v_cvt_f32_ubyte3 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76425   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76426   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76427   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76428   { 22194 /* v_cvt_f32_ubyte3 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76429   { 22194 /* v_cvt_f32_ubyte3 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76470   { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76471   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76472   { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76473   { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76474   { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76502   { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76503   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76504   { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76505   { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76506   { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76536   { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76537   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76538   { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76539   { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76540   { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76574   { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76575   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76576   { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76577   { 22313 /* v_cvt_norm_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76578   { 22313 /* v_cvt_norm_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76606   { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76607   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76608   { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76609   { 22332 /* v_cvt_norm_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76610   { 22332 /* v_cvt_norm_u16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76649   { 22351 /* v_cvt_off_f32_i4 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76650   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76651   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76652   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76653   { 22351 /* v_cvt_off_f32_i4 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76654   { 22351 /* v_cvt_off_f32_i4 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76722   { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76723   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76724   { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76725   { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76726   { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76754   { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76755   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76756   { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76757   { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76758   { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76788   { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76789   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76790   { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76791   { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76792   { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
76993   { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76994   { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
76995   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76996   { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76997   { 22899 /* v_exp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76998   { 22899 /* v_exp_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77032   { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77033   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77034   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77035   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77036   { 22909 /* v_exp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77037   { 22909 /* v_exp_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77083   { 22936 /* v_ffbh_i32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77084   { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77085   { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77086   { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77087   { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77109   { 22947 /* v_ffbh_u32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77110   { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77111   { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77112   { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77113   { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77135   { 22958 /* v_ffbl_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77136   { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77137   { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77138   { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77139   { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77168   { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77169   { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77170   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77171   { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77172   { 22969 /* v_floor_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77173   { 22969 /* v_floor_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77207   { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77208   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77209   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77210   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77211   { 22981 /* v_floor_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77212   { 22981 /* v_floor_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77346   { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77347   { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77348   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77349   { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77350   { 23168 /* v_fract_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77351   { 23168 /* v_fract_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77385   { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77386   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77387   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77388   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77389   { 23180 /* v_fract_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77390   { 23180 /* v_fract_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77423   { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77424   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77425   { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77426   { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77427   { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77457   { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77458   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77459   { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77460   { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77461   { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77502   { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77503   { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77504   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77505   { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77506   { 23264 /* v_frexp_mant_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77507   { 23264 /* v_frexp_mant_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77541   { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77542   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77543   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77544   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77545   { 23281 /* v_frexp_mant_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77546   { 23281 /* v_frexp_mant_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77675   { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77676   { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77677   { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77678   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77679   { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77680   { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77681   { 23439 /* v_ldexp_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
77682   { 23439 /* v_ldexp_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77736   { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77737   { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77738   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77739   { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77740   { 23501 /* v_log_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77741   { 23501 /* v_log_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77775   { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77776   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77777   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77778   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77779   { 23511 /* v_log_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77780   { 23511 /* v_log_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77848   { 23603 /* v_lshlrev_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77849   { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77850   { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77851   { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77852   { 23603 /* v_lshlrev_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
77853   { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77893   { 23667 /* v_lshrrev_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77894   { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77895   { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77896   { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77897   { 23667 /* v_lshrrev_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
77898   { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
77961   { 23715 /* v_mac_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77962   { 23715 /* v_mac_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
77963   { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77964   { 23715 /* v_mac_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77965   { 23715 /* v_mac_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77966   { 23715 /* v_mac_legacy_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
77967   { 23715 /* v_mac_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78101   { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78102   { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78103   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78104   { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78105   { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78106   { 24084 /* v_max_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78107   { 24084 /* v_max_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78143   { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78144   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78145   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78146   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78147   { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78148   { 24094 /* v_max_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78149   { 24094 /* v_max_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78199   { 24124 /* v_max_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78200   { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78201   { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78202   { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78203   { 24124 /* v_max_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78204   { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78247   { 24161 /* v_max_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78248   { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78249   { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78250   { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78251   { 24161 /* v_max_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78252   { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78390   { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78391   { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78392   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78393   { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78394   { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78395   { 24775 /* v_min_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78396   { 24775 /* v_min_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78432   { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78433   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78434   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78435   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78436   { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78437   { 24785 /* v_min_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78438   { 24785 /* v_min_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78488   { 24815 /* v_min_i32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78489   { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78490   { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78491   { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78492   { 24815 /* v_min_i32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78493   { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78536   { 24852 /* v_min_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78537   { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78538   { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78539   { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78540   { 24852 /* v_min_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78541   { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78559   { 24862 /* v_mov_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78560   { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78561   { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78562   { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78563   { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78585   { 24872 /* v_mov_fed_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78586   { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78587   { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78588   { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78589   { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78634   { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78635   { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78636   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78637   { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78638   { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78639   { 24989 /* v_mul_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78640   { 24989 /* v_mul_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78676   { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78677   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78678   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78679   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78680   { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78681   { 24999 /* v_mul_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78682   { 24999 /* v_mul_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78716   { 25032 /* v_mul_hi_i32_i24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78717   { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78718   { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78719   { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78720   { 25032 /* v_mul_hi_i32_i24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78721   { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78745   { 25062 /* v_mul_hi_u32_u24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78746   { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78747   { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78748   { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78749   { 25062 /* v_mul_hi_u32_u24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78750   { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78774   { 25079 /* v_mul_i32_i24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78775   { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78776   { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78777   { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78778   { 25079 /* v_mul_i32_i24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78779   { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78814   { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78815   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
78816   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78817   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78818   { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78819   { 25093 /* v_mul_legacy_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78820   { 25093 /* v_mul_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78861   { 25149 /* v_mul_u32_u24 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78862   { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78863   { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78864   { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78865   { 25149 /* v_mul_u32_u24 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78866   { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78890   { 25182 /* v_not_b32 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78891   { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78892   { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78893   { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78894   { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
78922   { 25202 /* v_or_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78923   { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78924   { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78925   { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78926   { 25202 /* v_or_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
78927   { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79159   { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79160   { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79161   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79162   { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79163   { 25609 /* v_rcp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79164   { 25609 /* v_rcp_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79198   { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79199   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79200   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79201   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79202   { 25619 /* v_rcp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79203   { 25619 /* v_rcp_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79246   { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79247   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79248   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79249   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79250   { 25639 /* v_rcp_iflag_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79251   { 25639 /* v_rcp_iflag_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79285   { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79286   { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79287   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79288   { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79289   { 25707 /* v_rndne_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79290   { 25707 /* v_rndne_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79324   { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79325   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79326   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79327   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79328   { 25719 /* v_rndne_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79329   { 25719 /* v_rndne_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79375   { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79376   { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79377   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79378   { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79379   { 25775 /* v_rsq_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79380   { 25775 /* v_rsq_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79414   { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79415   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79416   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79417   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79418   { 25785 /* v_rsq_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79419   { 25785 /* v_rsq_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79467   { 25863 /* v_sat_pk_u8_i16 */, 2 /* 1 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79468   { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79469   { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79470   { 25863 /* v_sat_pk_u8_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79471   { 25863 /* v_sat_pk_u8_i16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79509   { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79510   { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79511   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79512   { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79513   { 25906 /* v_sin_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79514   { 25906 /* v_sin_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79548   { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79549   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79550   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79551   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79552   { 25916 /* v_sin_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79553   { 25916 /* v_sin_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79584   { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79585   { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79586   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79587   { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79588   { 25926 /* v_sqrt_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79589   { 25926 /* v_sqrt_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79623   { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79624   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79625   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79626   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79627   { 25937 /* v_sqrt_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79628   { 25937 /* v_sqrt_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79663   { 25959 /* v_sub_co_ci_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79664   { 25959 /* v_sub_co_ci_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79665   { 25959 /* v_sub_co_ci_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79666   { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79667   { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
79668   { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79730   { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79731   { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79732   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79733   { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79734   { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79735   { 25988 /* v_sub_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
79736   { 25988 /* v_sub_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79772   { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79773   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79774   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79775   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79776   { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79777   { 25998 /* v_sub_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
79778   { 25998 /* v_sub_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79800   { 26067 /* v_sub_nc_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79801   { 26067 /* v_sub_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79802   { 26067 /* v_sub_nc_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79803   { 26067 /* v_sub_nc_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79804   { 26067 /* v_sub_nc_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
79805   { 26067 /* v_sub_nc_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79910   { 26156 /* v_subrev_co_ci_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79911   { 26156 /* v_subrev_co_ci_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79912   { 26156 /* v_subrev_co_ci_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79913   { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79914   { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
79915   { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
79977   { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79978   { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
79979   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79980   { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79981   { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79982   { 26191 /* v_subrev_f16 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
79983   { 26191 /* v_subrev_f16 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
80019   { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80020   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
80021   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80022   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80023   { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80024   { 26204 /* v_subrev_f32 */, 256 /* 8 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
80025   { 26204 /* v_subrev_f32 */, 64 /* 6 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
80043   { 26230 /* v_subrev_nc_u32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80044   { 26230 /* v_subrev_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80045   { 26230 /* v_subrev_nc_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80046   { 26230 /* v_subrev_nc_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80047   { 26230 /* v_subrev_nc_u32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
80048   { 26230 /* v_subrev_nc_u32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
80118   { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80119   { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
80120   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80121   { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80122   { 26314 /* v_trunc_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80123   { 26314 /* v_trunc_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
80157   { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80158   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmOModSI, AMFBS_HasSDWA10_isGFX10Plus },
80159   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80160   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80161   { 26326 /* v_trunc_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80162   { 26326 /* v_trunc_f32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
80201   { 26376 /* v_xnor_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80202   { 26376 /* v_xnor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80203   { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80204   { 26376 /* v_xnor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80205   { 26376 /* v_xnor_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
80206   { 26376 /* v_xnor_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },
80230   { 26398 /* v_xor_b32 */, 6 /* 1, 2 */, MCK_SDWAWithInt32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80231   { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80232   { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80233   { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80234   { 26398 /* v_xor_b32 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_HasSDWA10_isGFX10Plus },
80235   { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_HasSDWA10_isGFX10Plus },