reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

13112   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13114   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13116   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13118   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13122   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13124   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13126   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13128   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13130   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13132   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13134   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13136   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13138   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13140   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13142   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13144   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13146   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13148   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13150   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13152   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13154   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13156   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13158   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13160   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13162   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13164   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13166   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13168   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13170   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13172   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13174   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13176   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13202   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13204   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13206   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13208   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13210   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13212   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13214   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13216   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13218   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13220   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13222   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13224   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13226   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13228   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13230   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13232   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13236   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13238   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13240   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13242   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13244   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13246   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13248   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13250   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13252   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13254   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13256   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13258   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13260   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13262   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13264   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13266   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13268   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13270   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13272   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13274   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13276   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13278   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13280   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13282   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13284   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13286   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13288   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13290   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13292   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13294   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13296   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13298   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13300   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13302   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13304   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13306   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13308   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13310   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13312   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13314   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13316   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13318   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13320   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13322   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13324   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13326   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13328   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13330   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13332   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13334   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13336   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13338   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13340   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13342   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13344   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13346   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13348   { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13350   { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13352   { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13354   { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13356   { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13358   { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13360   { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13362   { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13364   { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13366   { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13368   { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13370   { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13372   { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13374   { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13376   { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13378   { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13380   { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13382   { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13384   { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13386   { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13388   { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13390   { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13392   { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13394   { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13396   { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13398   { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13400   { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13402   { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13404   { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13406   { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13408   { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13410   { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13412   { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13414   { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13416   { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13418   { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13420   { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13422   { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13424   { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13426   { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13428   { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13430   { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13432   { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13434   { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
30434   { 4992 /* global_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30435   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30438   { 4992 /* global_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30439   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30442   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30443   { 4992 /* global_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30446   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30447   { 4992 /* global_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30454   { 5032 /* global_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30455   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30458   { 5032 /* global_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30459   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30462   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30463   { 5032 /* global_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30466   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30467   { 5032 /* global_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30470   { 5053 /* global_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30471   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30474   { 5053 /* global_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30475   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30478   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30479   { 5053 /* global_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30482   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30483   { 5053 /* global_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30486   { 5071 /* global_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30487   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30490   { 5071 /* global_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30491   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30494   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30495   { 5071 /* global_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30498   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30499   { 5071 /* global_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30502   { 5092 /* global_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30503   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30506   { 5092 /* global_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30507   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30510   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30511   { 5092 /* global_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30514   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30515   { 5092 /* global_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30518   { 5114 /* global_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30519   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30522   { 5114 /* global_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30523   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30526   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30527   { 5114 /* global_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30530   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30531   { 5114 /* global_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30534   { 5139 /* global_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30535   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30538   { 5139 /* global_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30539   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30542   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30543   { 5139 /* global_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30546   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30547   { 5139 /* global_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30550   { 5157 /* global_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30551   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30554   { 5157 /* global_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30555   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30558   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30559   { 5157 /* global_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30562   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30563   { 5157 /* global_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30614   { 5309 /* global_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30615   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30618   { 5309 /* global_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30619   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30622   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30623   { 5309 /* global_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30626   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30627   { 5309 /* global_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30630   { 5327 /* global_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30631   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30634   { 5327 /* global_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30635   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30638   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30639   { 5327 /* global_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30642   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30643   { 5327 /* global_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30646   { 5348 /* global_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30647   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30650   { 5348 /* global_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30651   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30654   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30655   { 5348 /* global_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30658   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30659   { 5348 /* global_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30662   { 5365 /* global_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30663   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30666   { 5365 /* global_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30667   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30670   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30671   { 5365 /* global_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30674   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30675   { 5365 /* global_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30682   { 5410 /* global_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30683   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30686   { 5410 /* global_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30687   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30690   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30691   { 5410 /* global_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30694   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30695   { 5410 /* global_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30698   { 5429 /* global_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30699   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30702   { 5429 /* global_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30703   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30706   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30707   { 5429 /* global_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30710   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30711   { 5429 /* global_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30714   { 5451 /* global_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30715   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30718   { 5451 /* global_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30719   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30722   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30723   { 5451 /* global_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30726   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30727   { 5451 /* global_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30730   { 5470 /* global_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30731   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30734   { 5470 /* global_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30735   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30738   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30739   { 5470 /* global_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30742   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30743   { 5470 /* global_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30746   { 5492 /* global_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30747   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30750   { 5492 /* global_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30751   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30754   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30755   { 5492 /* global_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30758   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30759   { 5492 /* global_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30762   { 5510 /* global_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30763   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30766   { 5510 /* global_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30767   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30770   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30771   { 5510 /* global_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30774   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30775   { 5510 /* global_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30778   { 5531 /* global_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30779   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30782   { 5531 /* global_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30783   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30786   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30787   { 5531 /* global_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30790   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30791   { 5531 /* global_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30794   { 5550 /* global_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30795   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30798   { 5550 /* global_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30799   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30802   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30803   { 5550 /* global_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30806   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30807   { 5550 /* global_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30810   { 5572 /* global_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30811   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30814   { 5572 /* global_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30815   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30818   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30819   { 5572 /* global_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30822   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30823   { 5572 /* global_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30826   { 5591 /* global_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30827   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30830   { 5591 /* global_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30831   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30834   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30835   { 5591 /* global_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30838   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30839   { 5591 /* global_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30842   { 5613 /* global_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30843   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30846   { 5613 /* global_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30847   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30850   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30851   { 5613 /* global_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30854   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30855   { 5613 /* global_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30858   { 5632 /* global_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30859   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30862   { 5632 /* global_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30863   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30866   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30867   { 5632 /* global_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30870   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30871   { 5632 /* global_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30874   { 5654 /* global_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30875   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30878   { 5654 /* global_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30879   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30882   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30883   { 5654 /* global_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30886   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30887   { 5654 /* global_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30890   { 5672 /* global_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30891   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30894   { 5672 /* global_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30895   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30898   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30899   { 5672 /* global_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30902   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30903   { 5672 /* global_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30906   { 5693 /* global_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30907   { 5693 /* global_load_dword */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30908   { 5693 /* global_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30909   { 5693 /* global_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30914   { 5693 /* global_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30915   { 5693 /* global_load_dword */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30916   { 5693 /* global_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30917   { 5693 /* global_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30922   { 5711 /* global_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30923   { 5711 /* global_load_dwordx2 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30924   { 5711 /* global_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30925   { 5711 /* global_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30930   { 5711 /* global_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30931   { 5711 /* global_load_dwordx2 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30932   { 5711 /* global_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30933   { 5711 /* global_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30938   { 5731 /* global_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30939   { 5731 /* global_load_dwordx3 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30940   { 5731 /* global_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30941   { 5731 /* global_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30946   { 5731 /* global_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30947   { 5731 /* global_load_dwordx3 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30948   { 5731 /* global_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30949   { 5731 /* global_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30954   { 5751 /* global_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30955   { 5751 /* global_load_dwordx4 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30956   { 5751 /* global_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30957   { 5751 /* global_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30962   { 5751 /* global_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30963   { 5751 /* global_load_dwordx4 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30964   { 5751 /* global_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30965   { 5751 /* global_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30970   { 5771 /* global_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30971   { 5771 /* global_load_sbyte */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30972   { 5771 /* global_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30973   { 5771 /* global_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30978   { 5771 /* global_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30979   { 5771 /* global_load_sbyte */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30980   { 5771 /* global_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30981   { 5771 /* global_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30986   { 5789 /* global_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30987   { 5789 /* global_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30988   { 5789 /* global_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30989   { 5789 /* global_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30994   { 5789 /* global_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30995   { 5789 /* global_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30996   { 5789 /* global_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30997   { 5789 /* global_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31002   { 5811 /* global_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31003   { 5811 /* global_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31004   { 5811 /* global_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31005   { 5811 /* global_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31010   { 5811 /* global_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31011   { 5811 /* global_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31012   { 5811 /* global_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31013   { 5811 /* global_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31018   { 5836 /* global_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31019   { 5836 /* global_load_short_d16 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31020   { 5836 /* global_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31021   { 5836 /* global_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31026   { 5836 /* global_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31027   { 5836 /* global_load_short_d16 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31028   { 5836 /* global_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31029   { 5836 /* global_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31034   { 5858 /* global_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31035   { 5858 /* global_load_short_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31036   { 5858 /* global_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31037   { 5858 /* global_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31042   { 5858 /* global_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31043   { 5858 /* global_load_short_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31044   { 5858 /* global_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31045   { 5858 /* global_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31050   { 5883 /* global_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31051   { 5883 /* global_load_sshort */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31052   { 5883 /* global_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31053   { 5883 /* global_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31058   { 5883 /* global_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31059   { 5883 /* global_load_sshort */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31060   { 5883 /* global_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31061   { 5883 /* global_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31066   { 5902 /* global_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31067   { 5902 /* global_load_ubyte */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31068   { 5902 /* global_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31069   { 5902 /* global_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31074   { 5902 /* global_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31075   { 5902 /* global_load_ubyte */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31076   { 5902 /* global_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31077   { 5902 /* global_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31082   { 5920 /* global_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31083   { 5920 /* global_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31084   { 5920 /* global_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31085   { 5920 /* global_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31090   { 5920 /* global_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31091   { 5920 /* global_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31092   { 5920 /* global_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31093   { 5920 /* global_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31098   { 5942 /* global_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31099   { 5942 /* global_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31100   { 5942 /* global_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31101   { 5942 /* global_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31106   { 5942 /* global_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31107   { 5942 /* global_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31108   { 5942 /* global_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31109   { 5942 /* global_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31114   { 5967 /* global_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31115   { 5967 /* global_load_ushort */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31116   { 5967 /* global_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31117   { 5967 /* global_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31122   { 5967 /* global_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31123   { 5967 /* global_load_ushort */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31124   { 5967 /* global_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31125   { 5967 /* global_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31130   { 5986 /* global_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31131   { 5986 /* global_store_byte */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31132   { 5986 /* global_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31133   { 5986 /* global_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31138   { 5986 /* global_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31139   { 5986 /* global_store_byte */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31140   { 5986 /* global_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31141   { 5986 /* global_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31146   { 6004 /* global_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31147   { 6004 /* global_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31148   { 6004 /* global_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31149   { 6004 /* global_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31154   { 6004 /* global_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31155   { 6004 /* global_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31156   { 6004 /* global_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31157   { 6004 /* global_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31162   { 6029 /* global_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31163   { 6029 /* global_store_dword */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31164   { 6029 /* global_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31165   { 6029 /* global_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31170   { 6029 /* global_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31171   { 6029 /* global_store_dword */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31172   { 6029 /* global_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31173   { 6029 /* global_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31178   { 6048 /* global_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31179   { 6048 /* global_store_dwordx2 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31180   { 6048 /* global_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31181   { 6048 /* global_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31186   { 6048 /* global_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31187   { 6048 /* global_store_dwordx2 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31188   { 6048 /* global_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31189   { 6048 /* global_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31194   { 6069 /* global_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31195   { 6069 /* global_store_dwordx3 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31196   { 6069 /* global_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31197   { 6069 /* global_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31202   { 6069 /* global_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31203   { 6069 /* global_store_dwordx3 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31204   { 6069 /* global_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31205   { 6069 /* global_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31210   { 6090 /* global_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31211   { 6090 /* global_store_dwordx4 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31212   { 6090 /* global_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31213   { 6090 /* global_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31218   { 6090 /* global_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31219   { 6090 /* global_store_dwordx4 */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31220   { 6090 /* global_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31221   { 6090 /* global_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31226   { 6111 /* global_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31227   { 6111 /* global_store_short */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31228   { 6111 /* global_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31229   { 6111 /* global_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31234   { 6111 /* global_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31235   { 6111 /* global_store_short */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31236   { 6111 /* global_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31237   { 6111 /* global_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31242   { 6130 /* global_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31243   { 6130 /* global_store_short_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31244   { 6130 /* global_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31245   { 6130 /* global_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31250   { 6130 /* global_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31251   { 6130 /* global_store_short_d16_hi */, 64 /* 6 */, MCK_ImmDLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31252   { 6130 /* global_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31253   { 6130 /* global_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },