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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12876 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12879 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12882 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12885 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12888 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12891 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12894 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12897 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12900 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12903 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12906 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12909 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12912 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12915 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12918 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12921 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12948 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12951 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12954 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12957 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12960 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12963 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12966 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12969 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12972 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12975 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12978 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12981 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12984 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12987 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12990 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12993 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12996 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12999 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13002 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13005 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13008 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13011 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13014 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13017 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13020 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13023 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13026 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13029 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13032 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13035 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13038 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13041 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13044 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13047 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13050 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13053 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13056 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13059 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13062 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13065 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13068 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13079 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13082 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13089 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13092 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13097 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13100 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13103 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13106 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13109 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
29846 { 3983 /* flat_atomic_add */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29847 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29852 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29853 { 3983 /* flat_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29858 { 3999 /* flat_atomic_add_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29859 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29864 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29865 { 3999 /* flat_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29870 { 4018 /* flat_atomic_and */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29871 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29876 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29877 { 4018 /* flat_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29882 { 4034 /* flat_atomic_and_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29883 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29888 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29889 { 4034 /* flat_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29894 { 4053 /* flat_atomic_cmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29895 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29900 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29901 { 4053 /* flat_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29906 { 4073 /* flat_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29907 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29912 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29913 { 4073 /* flat_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29918 { 4096 /* flat_atomic_dec */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29919 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29924 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29925 { 4096 /* flat_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29930 { 4112 /* flat_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29931 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29936 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29937 { 4112 /* flat_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29990 { 4250 /* flat_atomic_inc */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29991 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29996 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29997 { 4250 /* flat_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30002 { 4266 /* flat_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30003 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30008 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30009 { 4266 /* flat_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30014 { 4285 /* flat_atomic_or */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30015 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30020 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30021 { 4285 /* flat_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30026 { 4300 /* flat_atomic_or_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30027 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30032 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30033 { 4300 /* flat_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30038 { 4318 /* flat_atomic_smax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30039 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30044 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30045 { 4318 /* flat_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30050 { 4335 /* flat_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30051 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30056 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30057 { 4335 /* flat_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30062 { 4355 /* flat_atomic_smin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30063 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30068 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30069 { 4355 /* flat_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30074 { 4372 /* flat_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30075 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30080 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30081 { 4372 /* flat_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30086 { 4392 /* flat_atomic_sub */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30087 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30092 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30093 { 4392 /* flat_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30098 { 4408 /* flat_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30099 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30104 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30105 { 4408 /* flat_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30110 { 4427 /* flat_atomic_swap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30111 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30116 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30117 { 4427 /* flat_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30122 { 4444 /* flat_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30123 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30128 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30129 { 4444 /* flat_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30134 { 4464 /* flat_atomic_umax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30135 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30140 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30141 { 4464 /* flat_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30146 { 4481 /* flat_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30147 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30152 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30153 { 4481 /* flat_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30158 { 4501 /* flat_atomic_umin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30159 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30164 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30165 { 4501 /* flat_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30170 { 4518 /* flat_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30171 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30176 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30177 { 4518 /* flat_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30182 { 4538 /* flat_atomic_xor */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30183 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30188 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30189 { 4538 /* flat_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30194 { 4554 /* flat_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30195 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30200 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30201 { 4554 /* flat_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30210 { 4573 /* flat_load_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30211 { 4573 /* flat_load_dword */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30212 { 4573 /* flat_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30213 { 4573 /* flat_load_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30222 { 4589 /* flat_load_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30223 { 4589 /* flat_load_dwordx2 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30224 { 4589 /* flat_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30225 { 4589 /* flat_load_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30234 { 4607 /* flat_load_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30235 { 4607 /* flat_load_dwordx3 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30236 { 4607 /* flat_load_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30237 { 4607 /* flat_load_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30246 { 4625 /* flat_load_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30247 { 4625 /* flat_load_dwordx4 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30248 { 4625 /* flat_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30249 { 4625 /* flat_load_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30258 { 4643 /* flat_load_sbyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30259 { 4643 /* flat_load_sbyte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30260 { 4643 /* flat_load_sbyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30261 { 4643 /* flat_load_sbyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30302 { 4745 /* flat_load_sshort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30303 { 4745 /* flat_load_sshort */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30304 { 4745 /* flat_load_sshort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30305 { 4745 /* flat_load_sshort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30314 { 4762 /* flat_load_ubyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30315 { 4762 /* flat_load_ubyte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30316 { 4762 /* flat_load_ubyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30317 { 4762 /* flat_load_ubyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30342 { 4821 /* flat_load_ushort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30343 { 4821 /* flat_load_ushort */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30344 { 4821 /* flat_load_ushort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30345 { 4821 /* flat_load_ushort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30354 { 4838 /* flat_store_byte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30355 { 4838 /* flat_store_byte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30356 { 4838 /* flat_store_byte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30357 { 4838 /* flat_store_byte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30374 { 4877 /* flat_store_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30375 { 4877 /* flat_store_dword */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30376 { 4877 /* flat_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30377 { 4877 /* flat_store_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30386 { 4894 /* flat_store_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30387 { 4894 /* flat_store_dwordx2 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30388 { 4894 /* flat_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30389 { 4894 /* flat_store_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30398 { 4913 /* flat_store_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30399 { 4913 /* flat_store_dwordx3 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30400 { 4913 /* flat_store_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30401 { 4913 /* flat_store_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30410 { 4932 /* flat_store_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30411 { 4932 /* flat_store_dwordx4 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30412 { 4932 /* flat_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30413 { 4932 /* flat_store_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30422 { 4951 /* flat_store_short */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30423 { 4951 /* flat_store_short */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30424 { 4951 /* flat_store_short */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30425 { 4951 /* flat_store_short */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },